Datasheet

USBDFxxW5 Application information
5/11
To have a good approximation of the remaining voltages at both V
in
and V
out
stages, we give
the typical dynamical resistance value R
d
. Taking into account the following hypothesis:
R
t
> R
d
, R
g
> R and R
load
> R
d
, gives these formulas::
The results of the calculation done for V
PP
= 8 kV, R
g
= 330 W (IEC61000-4-2 standard),
V
BR
= 7 V (typ.) and R
d
= 1 Ω (typ.) give:
V
input
= 31.2 V
V
output
= 7.95 V
This confirms the very low remaining voltage across the device to be protected. It is also
important to note that in this approximation the parasitic inductance effect was not taken into
account. This could be few tenths of volts during few ns at the V
in
side. This parasitic effect
is not present at the V
out
side due the low current involved after the resistance R.
The measurements results shown below show very clearly (Figure 7.) the high efficiency of
the ESD protection :
● no influence of the parasitic inductances on Vout stage
● output clamping voltage very close to V
BR
(positive strike) and -V
F
(negative strike)
Figure 6. Measurement board
V=
input
V=
output
R.V + R.V
gBR d g
R.V + R .V
t BR d inpu
t
R
g
R
t
TEST BOARD
ESD
SURGE
15 kV
Air
Discharge
Vin Vout
UD1