Datasheet

DocID4078 Rev 3 13/19
TS556 Application information
19
4 Application information
4.1 Monostable operation
In monostable mode, the timer operates like a one-shot generator. Referring to Figure 2, the
external capacitor is initially held discharged by a transistor inside the timer, as shown in
Figure 4.
Figure 4. Application schematic
The circuit triggers on a negative-going input signal when the level reaches 1/3 V
CC
. Once
triggered, the circuit remains in this state until the set time has elapsed, even if it is triggered
again during this interval. The duration of the output HIGH state is given by t = 1.1 R x C.
It can be noticed that since the charge rate and the threshold level of the comparator are
both directly proportional to the supply voltage, the timing interval is independent of the
supply. Applying a negative pulse simultaneously to the reset terminal (pin 4) and the trigger
terminal (pin 2) during the timing cycle, discharges the external capacitor and causes the
cycle to start over. The timing cycle now starts on the positive edge of the reset pulse. While
the reset pulse is applied, the output is driven to the LOW state.
When a negative trigger pulse is applied to pin 2, the flip-flop is set, releasing the short
circuit across the external capacitor and driving the output HIGH. The voltage across the
capacitor increases exponentially with the time constant τ = R x C.
When the voltage across the capacitor equals 2/3 V
CC
, the comparator resets the flip-flop
which then discharges the capacitor rapidly and drives the output to its LOW state.
Figure 5 shows the actual waveforms generated in this mode of operation. When reset is
not used, it should be tied high to avoid any possible or false triggering.
Figure 5. Timing diagram
V
CC
Reset
Trigger
Out
R
C
Control Voltage
0.01 F
1/2
TS556
CAPACITOR VOLTAGE = 2.0V/div
t = 0.1 ms / div
INPUT = 2.0V/div
OUTPUT VOLTAGE = 5.0V/div
R = 9.1k , C = 0.01 F , R = 1.0k
L