Datasheet

Electrical characteristics STM8S105x4/6
82/121 DocID14771 Rev 15
Figure 41. SPI timing diagram where slave mode and CPHA = 0
1. Measurement points are at CMOS levels: 0.3 V
DD
and 0.7 V
DD
.
Figure 42. SPI timing diagram where slave mode and CPHA = 1
1. Measurement points are at CMOS levels: 0.3 V
DD
and 0.7 V
DD
.
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