Datasheet

DocID14771 Rev 15 45/121
STM8S105x4/6 Interrupt vector mapping
50
20 UART2 Tx complete - - 0x00 8058
21 UART2
Receive register
DATA FULL
- - 0x00 805C
22 ADC1
ADC1 end of
conversion/ analog
watchdog interrupt
- - 0x00 8060
23 TIM4
TIM4 update/
overflow
- - 0x00 8064
24 Flash EOP/WR_PG_DIS - - 0x00 8068
Reserved
0x00 806C to
0x00 807C
1. Except PA1.
Table 10. Interrupt mapping (continued)
IRQ no. Source block Description
Wakeup from
halt mode
Wakeup from
active-halt mode
Vector address