Datasheet

DocID14771 Rev 15 43/121
STM8S105x4/6 Memory and register map
50
0x00 7F90
DM
DM_BK1RE
DM breakpoint 1 register
extended byte
0xFF
0x00 7F91 DM_BK1RH
DM breakpoint 1 register
high byte
0xFF
0x00 7F92 DM_BK1RL
DM breakpoint 1 register
low byte
0xFF
0x00 7F93 DM_BK2RE
DM breakpoint 2 register
extended byte
0xFF
0x00 7F94 DM_BK2RH
DM breakpoint 2 register
high byte
0xFF
0x00 7F95 DM_BK2RL
DM breakpoint 2 register
low byte
0xFF
0x00 7F96 DM_CR1
DM debug module control
register 1
0x00
0x00 7F97 DM_CR2
DM debug module control
register 2
0x00
0x00 7F98 DM_CSR1
DM debug module
control/status register 1
0x10
0x00 7F99 DM_CSR2
DM debug module
control/status register 2
0x00
0x00 7F9A DM_ENFCTR DM enable function register 0xFF
0x00 7F9B to 0x00 7F9F Reserved area (5 byte)
1. Accessible by debug module only.
Table 9. CPU/SWIM/debug module/interrupt controller registers (continued)
Address Block Register label Register name
Reset
status