Datasheet

DocID14771 Rev 15 35/121
STM8S105x4/6 Memory and register map
50
0x00 50C3
CLK
CLK_CMSR Clock master status register 0xE1
0x00 50C4 CLK_SWR Clock master switch register 0xE1
0x00 50C5 CLK_SWCR Clock switch control register 0xXX
0x00 50C6 CLK_CKDIVR Clock divider register 0x18
0x00 50C7 CLK_PCKENR1
Peripheral clock gating
register 1
0xFF
0x00 50C8 CLK_CSSR Clock security system register 0x00
0x00 50C9 CLK_CCOR
Configurable clock control
register
0x00
0x00 50CA CLK_PCKENR2
Peripheral clock gating
register 2
0xFF
0x00 50CC CLK_HSITRIMR
HSI clock calibration trimming
register
0x00
0x00 50CD CLK_SWIMCCR SWIM clock control register 0bXXXX XXX0
0x00 50CE to 0x00 50D0 Reserved area (3 byte)
0x00 50D1
WWDG
WWDG_CR WWDG control register 0x7F
0x00 50D2 WWDG_WR WWDR window register 0x7F
0x00 50D3 to 00 50DF Reserved area (13 byte)
0x00 50E0
IWDG
IWDG_KR IWDG key register 0xXX
(2)
0x00 50E1 IWDG_PR IWDG prescaler register 0x00
0x00 50E2 IWDG_RLR IWDG reload register 0xFF
0x00 50E3 to 0x00 50EF Reserved area (13 byte)
0x00 50F0
AWU
AWU_CSR1 AWU control/status register 1 0x00
0x00 50F1 AWU_APR
AWU asynchronous prescaler
buffer register
0x3F
0x00 50F2 AWU_TBR
AWU timebase selection
register
0x00
0x00 50F3 BEEP BEEP_CSR BEEP control/status register 0x1F
0x00 50F4 to 0x00 50FF Reserved area (12 byte)
0x00 5200
SPI
SPI_CR1 SPI control register 1 0x00
0x00 5201 SPI_CR2 SPI control register 2 0x00
0x00 5202 SPI_ICR SPI interrupt control register 0x00
0x00 5203 SPI_SR SPI status register 0x02
0x00 5204 SPI_DR SPI data register 0x00
0x00 5205 SPI_CRCPR SPI CRC polynomial register 0x07
0x00 5206 SPI_RXCRCR SPI Rx CRC register 0xFF
0x00 5207 SPI_TXCRCR SPI Tx CRC register 0xFF
Table 8. General hardware register map (continued)
Address Block Register label Register name Reset status