Datasheet
DocID14771 Rev 15 29/121
STM8S105x4/6 Pinout and pin description
30
40 36 - - PE0/ CLK_CCO I/O X X X HS O3 X X Port E0
Configura
ble clock
output
-
41 37 25 30
PD0/
TIM3_CH2
[TIM1_BKIN]
[CLK_CCO]
I/O X
X X HS O3 X X Port D0
Timer 3 -
channel 2
TIM1_BK
IN
[AFR3]/
CLK_CC
O [AFR2]
42 38 26 31 PD1/ SWIM
(5)
I/O X XX XHSO4X Port D1
SWIM
data
interface
-
43 39 27 32
PD2/
TIM3_CH1
[TIM2_CH3]
I/O X
X X HS O3 X X Port D2
Timer 3 -
channel 1
TIM2_CH
3 [AFR1]
44 40 28 1
PD3/
TIM2_CH2
[ADC_ETR]
I/O X
X X HS O3 X X Port D3
Timer 2 -
channel 2
ADC_ET
R [AFR0]
45 41 29 2
PD4/
TIM2_CH1
[BEEP]
I/O X
X X HS O3 X X Port D4
Timer 2 -
channel 1
BEEP
output
[AFR7]
46 42 30 3
PD5/
UART2_TX
I/O X
XX -O1XXPort D5
UART2
data
transmit
-
47 43 31 4
PD6/
UART2_RX
I/O X
XX -O1XX Port D6
UART2
data
receive
-
48 44 32 5
PD7/ TLI
[TIM1_CH4
I/O X
XX -O1XX Port D7
Top level
interrupt
TIM1_CH
4 [AFR4]
1. A pull-up is applied to PF4 during the reset phase. This pin is input floating after reset release.
2. AIN12 is not selectable in ADC scan mode or with analog watchdog.
3. In 44-pin package, AIN9 cannot be used by ADC scan mode.
4. In the open-drain output column, âTâ defines a true open-drain I/O (P-buffer, weak pull-up and protection diode to V
DD
are
not implemented).
5. The PD1 pin is in input pull-up during the reset phase and after internal reset release.
Table 5. STM8S105x4/6 pin description (continued)
Pin number
Pin name Type
Input Output
Main
function
(after
reset)
Default
alternate
function
Alternate
function
after
remap
[option
bit]
LQFP48
LQFP44
LQFP32/UFQFPN32
SDIP32
Floating
wpu
Ext. interrupt
High sink
Speed
OD
PP