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ManualsBrandsST ManualsEmbedded Processors & ControllersMicrocontroller 8bit 32KB LQFP

This is information on a product in full production.

September 2015 DocID14771 Rev 15 1/121

STM8S105C4/6 STM8S105K4/6

STM8S105S4/6

Access line, 16 MHz STM8S 8-bit MCU, up to 32 Kbyte Flash,

integrated EEPROM, 10-bit ADC, timers, UART, SPI, I²C

Datasheet - production data

Features

Core

 16 MHz advanced STM8 core with Harvard

architecture and 3-stage pipeline

 Extended instruction set

Memories

 Program memory: up to 32 Kbyte Flash; data

retention 20 years at 55 °C after 10 kcycle

 Data memory: up to 1 Kbyte true data

EEPROM; endurance 300 kcycle

 RAM: up to 2 Kbyte

Clock, reset and supply management

 2.95 to 5.5 V operating voltage

 Flexible clock control, 4 master clock sources

– Low power crystal resonator oscillator

– External clock input

– Internal, user-trimmable 16 MHz RC

– Internal low-power 128 kHz RC

 Clock security system with clock monitor

 Power management:

– Low-power modes (wait, active-halt, halt)

– Switch-off peripheral clocks individually

 Permanently active, low-consumption power-

on and power-down reset

Interrupt management

 Nested interrupt controller with 32 interrupts

 Up to 37 external interrupts on 6 vectors

Timers

 Advanced control timer: 16-bit, 4 CAPCOM

channels, 3 complementary outputs, dead-time

insertion and flexible synchronization

 2x16-bit general purpose timer, with 2+3

CAPCOM channels (IC, OC or PWM)

 8-bit basic timer with 8-bit prescaler

 Auto wake-up timer

 Window watchdog and independent watchdog

timers

Communication interfaces

 UART with clock output for synchronous

operation, SmartCard, IrDA, LIN master mode

 SPI interface up to 8 Mbit/s

 I2C interface up to 400 kbit/s

Analog to digital converter (ADC)

 10-bit, ±1 LSB ADC with up to 10 multiplexed

channels, scan mode and analog watchdog

I/Os

 Up to 38 I/Os on a 48-pin package including 

16 high sink outputs

 Highly robust I/O design, immune against

current injection

Unique ID

 96-bit unique key for each device

LQFP48 (7x7 mm)

LQFP44 (10x10 mm)

LQFP32 (7x7 mm)

UFQFPN32 (5x5 mm)





SDIP32 400ml

www.st.com

Summary of content (121 pages)

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STM8S105C4/6 STM8S105K4/6 STM8S105S4/6 Access line, 16 MHz STM8S 8-bit MCU, up to 32 Kbyte Flash, integrated EEPROM, 10-bit ADC, timers, UART, SPI, I²C Datasheet - production data Features Core  16 MHz advanced STM8 core with Harvard architecture and 3-stage pipeline  Extended instruction set LQFP48 (7x7 mm) LQFP44 (10x10 mm) LQFP32 (7x7 mm) Memories  Program memory: up to 32 Kbyte Flash; data retention 20 years at 55 °C after 10 kcycle  Data memory: up to 1 Kbyte true data EEPROM; endurance 30
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Contents STM8S105x4/6 Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4 Product overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5 4.
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STM8S105x4/6 Contents 6.2.3 CPU/SWIM/debug module/interrupt controller registers . . . . . . . . . . . . 42 7 Interrupt vector mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 8 Option byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 8.1 Alternate function remapping bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 9 Unique ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Contents STM8S105x4/6 11.5 12 13 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 12.1 Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 12.2 Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . . . 107 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 13.1 14 SDIP32 package information . . . . . . . . . . . . . . .
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STM8S105x4/6 List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45. Table 46. Table 47.
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List of tables Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. 6/121 STM8S105x4/6 ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package  mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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STM8S105x4/6 List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42. Figure 43.
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List of figures Figure 49. Figure 50. Figure 51. Figure 52. Figure 53. Figure 54. Figure 55. Figure 56. Figure 57. Figure 58. Figure 59. Figure 60. Figure 61. 8/121 STM8S105x4/6 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 LQFP48 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 LQFP44 - 44-pin, 10 x 10 mm low-profile quad flat package outline . . . . . . . . . . .
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STM8S105x4/6 1 Introduction Introduction This datasheet contains the description of the device features, pinout, electrical characteristics, mechanical data and ordering information.  For complete information on the STM8S microcontroller memory, registers and peripherals, please refer to the STM8S microcontroller family reference manual (RM0016).  For information on programming, erasing and protection of the internal Flash memory please refer to the STM8S Flash programming manual (PM0051).
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Description 2 STM8S105x4/6 Description The STM8S105x4/6 access line 8-bit microcontrollers offer from 16 to 32 Kbyte Flash program memory, plus integrated true data EEPROM. The STM8S microcontroller family reference manual (RM0016) refers to devices in this family as medium-density. All devices of the STM8S105x4/6 access line provide the following benefits: reduced system cost, performance and robustness, short development cycles, and product longevity.
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STM8S105x4/6 Description Table 1. STM8S105x4/6 access line features Device STM8S105C6 STM8S105C4 STM8S105S6 STM8S105S4 STM8S105K6 STM8S105K4 Pin count 48 48 44 44 32 32 Maximum number of GPIOs 38 38 34 34 25 25 Ext.
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Block diagram 3 STM8S105x4/6 Block diagram Figure 1. STM8S105x4/6 block diagram 5HVHW EORFN ;7$/ 0+] &ORFN FRQWUROOHU 5HVHW 5HVHW 5& LQW 0+] %25 325 'HWHFWRU 5& LQW N+] &ORFN WR SHULSKHUDOV DQG FRUH :LQGRZ :'* 670 FRUH ,QGHSHQGHQW :'* 6LQJOH ZLUH GHEXJ LQWHUI 8S WR .E\WH 3URJUDP )ODVK 'HEXJ 6:,0 .ELW V , & 0ELW V 63, 0DVWHU VODYH DXWRV\QFKUR /,1 PDVWHU 63, HPXO $GGUHVV DQG GDWD EXV .E\WH GDWD ((3520 8S WR .E\WH 5$0 %RRW 520 ELW DGYDQFHG FRQWURO WLP
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STM8S105x4/6 4 Product overview Product overview The following section provides an overview of the basic features of the device functional modules and peripherals. For more detailed information please refer to the corresponding family reference manual (RM0016). 4.1 Central processing unit STM8 The 8-bit STM8 core is designed for code efficiency and performance.
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Product overview 4.2 STM8S105x4/6 Single wire interface module (SWIM) and debug module (DM) The single wire interface module and debug module permits non-intrusive, real-time incircuit debugging and fast memory programming. SWIM Single wire interface module for direct access to the debug module and memory programming. The interface can be activated in all device operation modes. The maximum data transmission speed is 145 bytes/ms.
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STM8S105x4/6 Product overview The size of the UBC is programmable through the UBC option byte, in increments of 1 page (512 byte) by programming the UBC option byte in ICP mode. This divides the program memory into two areas:  Main program memory: up to 32 Kbyte minus UBC  User-specific boot code (UBC): Configurable up to 32 Kbyte The UBC area remains write-protected during in-application programming. This means that the MASS keys do not unlock the UBC area.
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Product overview 4.5 STM8S105x4/6 Clock controller The clock controller distributes the system clock (fMASTER) coming from different oscillators to the core and the peripherals. It also manages clock gating for low power modes and ensures clock robustness. Features  Clock prescaler: to get the best compromise between speed and current consumption the clock frequency to the CPU and peripherals can be adjusted by a programmable prescaler.
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STM8S105x4/6 4.6 Product overview Power management For efficient power management, the application can be put in one of four different lowpower modes. You can configure each mode to obtain the best compromise between lowest power consumption, fastest start-up time and available wakeup sources. 4.7  Wait mode: In this mode, the CPU is stopped, but peripherals are kept running. The wakeup is performed by an internal or external interrupt or reset.
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Product overview STM8S105x4/6 The IWDG time base spans from 60 µs to 1 s. 4.8 4.9 Auto wakeup counter  Used for auto wakeup from active halt mode,  Clock source: Internal 128 kHz internal low frequency RC oscillator or external clock,  LSI clock can be internally connected to TIM1 input capture channel 1 for calibration. Beeper The beeper function outputs a signal on the BEEP pin for sound generation. The signal is in the range of 1, 2 or 4 kHz.
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STM8S105x4/6 4.12 Product overview TIM4 - 8-bit basic timer  8-bit auto reload, adjustable prescaler ratio to any power of 2 from 1 to 128  Clock source: CPU clock  Interrupt source: 1 x overflow/update Table 3.
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Product overview 4.14 STM8S105x4/6 Communication interfaces The following communication interfaces are implemented: 4.14.1  UART1: Full feature UART, synchronous mode, SPI master mode, Smartcard mode, IrDA mode, single wire mode, LIN2.
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STM8S105x4/6 Product overview LIN slave mode 4.14.2 4.14.
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Pinout and pin description 5 STM8S105x4/6 Pinout and pin description Table 4.
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STM8S105x4/6 Pinout and pin description 3* 3* 3& +6 63,B0,62 3& +6 63,B026, 9'',2B 966,2B 3& +6 63,B6&. 3& +6 7,0 B&+ 3& +6 7,0 B&+ 3& +6 7,0 B&+ 3& +6 7,0 B&+ 8$57 B&.
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Pinout and pin description STM8S105x4/6 3( +6 &/.B&&2 3( 7 , &B6&/ 3( 7 , &B6'$ 3' +6 6:,0 3' +6 7,0 B&+ >7,0 B%.,1@ >&/.B&&2@ 3' 7/, >7,0 B&+ @ 3' 8$57 B5; 3' 8$57 B7; 3' +6 7,0 B&+ >%((3@ 3' +6 7,0 B&+ >$'&B(75@ 3' +6 7,0 B&+ >7,0 B&+ @ Figure 4.
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STM8S105x4/6 Pinout and pin description 3' 7/, >7,0 B&+ @ 3' 8$57 B5; 3' 8$57 B7; 3' +6 7,0 B&+ >%((3@ 3' +6 7,0 B&+ >$'&B(75@ 3' +6 7,0 B&+ >7,0 B&+ @ 3' +6 6:,0 3' +6 7,0 B&+ >7,0 B%.,1@ >&/.B&&2@ Figure 5.
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Pinout and pin description STM8S105x4/6 Figure 6. SDIP32 pinout $'&B(75 7,0 B&+ +6 3' >%((3@ 7,0 B&+ +6 3' 8$57 B7; 3' 8$57 B5; 3' >7,0 B&+ @ 7/, 3' 1567 26&,1 3$ 26&287 3$ 966 9&$3 9'' 9'',2 $,1 3) 9''$ 966$ >, &B6'$@ $,1 3% 3' +6 7,0 B&+ >7,0 B&+ @ 3' +6 6:,0 3' +6 7,0 B&+ >7,0 B%.,1@ >&/.B&&2@ 3& +6 63,B0,62 3& +6 63,B026, 3& +6 63,B6&.
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STM8S105x4/6 Pinout and pin description Table 5. STM8S105x4/6 pin description (continued) Output LQFP32/UFQFPN32 SDIP32 Pin name Floating wpu Ext.
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Pinout and pin description STM8S105x4/6 Table 5. STM8S105x4/6 pin description (continued) 25 23 17 PP PE6/ AIN9 OD - Speed - High sink 22 Ext.
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STM8S105x4/6 Pinout and pin description Table 5. STM8S105x4/6 pin description (continued) I/O X X X I/O X X X PP PE0/ CLK_CCO OD - Speed - High sink 36 Ext.
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Pinout and pin description 5.1 STM8S105x4/6 Alternate function remapping As shown in the rightmost column of the pin description table, some alternate functions can be remapped at different I/O ports by programming one of eight AFR (alternate function remap) option bits. When the remapping option is active, the default alternate function is no longer available. To use an alternate function, the corresponding peripheral must be enabled in the peripheral registers.
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STM8S105x4/6 Memory and register map 6 Memory and register map 6.1 Memory map Figure 7. Memory map [ 5$0 .E\WH [ )) E\WH VWDFN 5HVHUYHG [ [ )) [ [ )) [ .E\WH GDWD ((3520 5HVHUYHG 2SWLRQ E\WHV [ ) [ 5HVHUYHG [ ))) [ *3,2 DQG SHULSK UHJ [ )) [ 5HVHUYHG [ ))) [ [ )) [ [ ()) [ ) [ ))) [ .E\WH ERRW 520 5HVHUYHG &38 6:,0 GHEXJ ,7& UHJLVWHUV LQWHUUXSW YHF
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Memory and register map STM8S105x4/6 Table 6. Flash, data EEPROM and RAM boundary address Memory area Flash program memory Size (byte) Start address End address 32 K 0x00 8000 0x00 FFFF 16 K 0x00 8000 0x00 BFFF 2K 0x00 0000 0x00 07FF 1024 0x00 4000 0x00 43FF RAM Data EEPROM 6.2 Register map 6.2.1 I/O port hardware register map Table 7.
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STM8S105x4/6 Memory and register map Table 7.
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Memory and register map 6.2.2 STM8S105x4/6 General hardware register map Table 8.
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STM8S105x4/6 Memory and register map Table 8.
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Memory and register map STM8S105x4/6 Table 8.
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STM8S105x4/6 Memory and register map Table 8.
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Memory and register map STM8S105x4/6 Table 8.
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STM8S105x4/6 Memory and register map Table 8.
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Memory and register map STM8S105x4/6 Table 8.
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STM8S105x4/6 Memory and register map Table 8.
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Memory and register map 6.2.3 STM8S105x4/6 CPU/SWIM/debug module/interrupt controller registers Table 9.
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STM8S105x4/6 Memory and register map Table 9.
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Interrupt vector mapping 7 STM8S105x4/6 Interrupt vector mapping Table 10. Interrupt mapping IRQ no.
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STM8S105x4/6 Interrupt vector mapping Table 10. Interrupt mapping (continued) IRQ no. Source block Wakeup from halt mode Description Wakeup from active-halt mode Vector address 20 UART2 Tx complete - - 0x00 8058 21 UART2 Receive register DATA FULL - - 0x00 805C 22 ADC1 ADC1 end of conversion/ analog watchdog interrupt - 0x00 8060 23 TIM4 TIM4 update/ overflow - - 0x00 8064 24 Flash EOP/WR_PG_DIS - - 0x00 8068 0x00 806C to 0x00 807C Reserved 1. Except PA1.
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Option byte 8 STM8S105x4/6 Option byte Option byte contain configurations for device hardware features as well as the memory protection of the device. They are stored in a dedicated block of the memory. Except for the ROP (read-out protection) byte, each option byte has to be stored twice, in a regular form (OPTx) and a complemented one (NOPTx) for redundancy. Option byte can be modified in ICP mode (via SWIM) by accessing the EEPROM address shown in the table below.
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STM8S105x4/6 Option byte Table 11. Option byte (continued) Addr. Option name 0x487E Option byte no. Option bits 7 6 5 4 3 2 1 0 Factory default setting OPTBL BL[7:0] 0x00 NOPTBL NBL[7:0] 0xFF Bootloader 0x487F Table 12. Option byte description Option byte no.
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Option byte STM8S105x4/6 Table 12. Option byte description (continued) Option byte no.
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STM8S105x4/6 8.1 Option byte Alternate function remapping bits Table 13. Alternate function remapping bits [7:0] of OPT2 Description(1) Option byte no. OPT2 AFR7 Alternate function remapping option 7 0: AFR7 remapping option inactive: Default alternate functions.(2) 1: Port D4 alternate function = BEEP. AFR6 Alternate function remapping option 6 0: AFR6 remapping option inactive: Default alternate function.(2) 1: Port B5 alternate function = I2C_SDA; port B4 alternate function = I2C_SCL.
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Unique ID 9 STM8S105x4/6 Unique ID The devices feature a 96-bit unique device identifier which provides a reference number that is unique for any device and in any context. The 96 bits of the identifier can never be altered by the user. The unique device identifier can be read in single byte and may then be concatenated using a custom algorithm.
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STM8S105x4/6 Electrical characteristics 10 Electrical characteristics 10.1 Parameter conditions Unless otherwise specified, all voltages are referred to VSS. 10.1.1 Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at TA = 25 °C, and TA = TAmax (given by the selected temperature range).
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Electrical characteristics 10.1.5 STM8S105x4/6 Loading capacitor The loading conditions used for pin parameter measurement are shown in Figure 9. Figure 9. Pin loading conditions 670 6 3,1 S) 06Y 9 10.1.6 Pin input voltage The input voltage measurement on a pin of the device is described in Figure 10. Figure 10.
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STM8S105x4/6 10.2 Electrical characteristics Absolute maximum ratings Stresses above those listed as ‘absolute maximum ratings’ may cause permanent damage to the device. This is a stress rating only and functional operation of the device under these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Table 15. Voltage characteristics Symbol Min Max Unit -0.3 6.5 V VSS - 0.3 6.5 VSS - 0.3 VDD + 0.
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Electrical characteristics STM8S105x4/6 3. I/O pins used simultaneously for high current source/sink must be uniformly spaced around the package between the VDDIO/VSSIO pins. 4. IINJ(PIN) must never be exceeded. This condition is implicitly insured if VIN maximum is respected. If VIN maximum cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive injection is induced by VIN > VDD while a negative injection is induced by VIN < VSS.
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STM8S105x4/6 Electrical characteristics Table 18. General operating conditions (continued) Symbol Parameter Conditions Min Max TA Ambient temperature for suffix 6 version Maximum power dissipation -40 85 TA Ambient temperature for suffix 3 version Maximum power dissipation -40 125 TJ Junction temperature range Suffix 6 version -40 105 Suffix 3 version -40 130 Unit °C 1.
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Electrical characteristics STM8S105x4/6 Table 19. Operating conditions at power-up/power-down (continued) Symbol Parameter Conditions Min Typ Max VIT+ Power-on reset threshold - 2.65 2.8 2.95 VIT- Brown-out reset threshold - 2.58 2.65 2.88 VHYS(BOR) Brown-out reset hysteresis - - 70 - V 1. Guaranteed by design, not tested in production.
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STM8S105x4/6 10.3.1 Electrical characteristics VCAP external capacitor The stabilization for the main regulator is achieved by connecting an external capacitor CEXT to the VCAP pin. CEXT is specified in Table 18. Care should be taken to limit the series inductance to less than 15 nH. Figure 12. External capacitor CEXT (6/ & (65 5/HDN 06Y 9 1. ESR is the equivalent series resistance and ESL is the equivalent inductance. 10.3.
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Electrical characteristics STM8S105x4/6 Table 21. Total current consumption with code execution in run mode at VDD = 3.3 V Symbol Typ Max(1) HSE crystal osc. (16 MHz) 2.8 - HSE user ext. clock (16 MHz) 2.6 3.2 HSI RC osc. (16 MHz) 2.5 3.2 HSE user ext. clock (16 MHz) 1.6 2.2 HSI RC osc. (16 MHz) 1.3 2.0 fCPU = fMASTER /128 = 15.625 kHz HSI RC osc. (16 MHz/8) 0.75 - fCPU = fMASTER = 128 kHz LSI RC osc. (128 kHz) 0.55 - HSE crystal osc. (16 MHz) 7.3 - HSE user ext.
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STM8S105x4/6 Electrical characteristics Table 23. Total current consumption in wait mode at VDD = 3.3 V Symbol Typ Max(1) HSE crystal osc. (16 MHz) 1.75 - HSE user ext. clock (16 MHz) 1.55 2.0 HSI RC osc. (16 MHz) 1.5 1.9 fCPU = fMASTER /128 = 125 kHz HSI RC osc. (16 MHz) 1.3 - fCPU = fMASTER /s128 = 15.625 kHz HSI RC osc. (16 MHz/8)(2) 0.7 - fCPU = fMASTER = 128 kHz LSI RC osc. (128 kHz) 0.
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Electrical characteristics STM8S105x4/6 Table 25. Total current consumption in active halt mode at VDD = 3.3 V Conditions Symbol Parameter IDD(AH) Supply current in active halt mode Main voltage regulator (MVR)(2) On Off 1. Typ Flash mode(3) Clock source Max at Max at Unit 85 °C(1) 85 °C(1) Operating mode HSE crystal osc. (16 MHz) 680 - - Operating mode LSI RC osc. (128 kHz) 200 320 400 Power down mode HSE crystal osc. (16 MHz) 630 - - Power down mode LSI RC osc.
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STM8S105x4/6 Electrical characteristics Low power mode wakeup times Table 28. Wakeup times Typ Max(1) - See note(3) 0.
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Electrical characteristics STM8S105x4/6 HSI internal RC/fCPU= fMASTER = 16 MHz, VDD = 5 V Table 30. Peripheral current consumption Symbol Parameter Typ IDD(TIM1) TIM1 supply current (1) 230 IDD(TIM2) TIM2 supply current(1) 115 IDD(TIM3) TIM3 supply current (1) 90 TIM4 supply current (1) IDD(TIM4) IDD(UART2) UART2 supply current IDD(SPI) SPI supply current (2) IDD(I2C) current(2) I2C supply IDD(ADC1) 30 (2) ADC1 supply current when 110 Unit µA 45 65 converting(3) 955 1.
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STM8S105x4/6 Electrical characteristics Figure 14. Typ IDD(RUN) vs. fCPU HSE user external clock, VDD = 5 V Figure 15. Typ IDD(RUN) vs.
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Electrical characteristics STM8S105x4/6 Figure 16. Typ IDD(WFI) vs. VDD HSE external clock, fCPU = 16 MHz Figure 17. Typ IDD(WFI) vs.
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STM8S105x4/6 Electrical characteristics Figure 18. Typ IDD(WFI) vs. VDD HSI RC osc.
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Electrical characteristics 10.3.3 STM8S105x4/6 External clock sources and timing characteristics HSE user external clock Subject to general operating conditions for VDD and TA. Table 31. HSE user external clock characteristics Symbol Parameter Conditions Min Max Unit MHz fHSE_ext User external clock source frequency - 0 16 VHSEH(1) OSCIN input pin high level voltage - 0.7 x VDD VDD + 0.3 V VHSEL(1) OSCIN input pin low level voltage - VSS 0.
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STM8S105x4/6 Electrical characteristics HSE crystal/ceramic resonator oscillator The HSE clock can be supplied with a 1 to 16 MHz crystal/ceramic resonator oscillator. All the information given in this paragraph is based on characterization results with specified typical external components. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time.
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Electrical characteristics STM8S105x4/6 Figure 20.
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STM8S105x4/6 10.3.4 Electrical characteristics Internal clock sources and timing characteristics Subject to general operating conditions for VDD and TA. High speed internal RC oscillator (HSI) Table 33. HSI oscillator characteristics Symbol fHSI Parameter Conditions Min Typ Max Unit - - 16 - MHz - - 1(2) VDD V, TA  25 °C(3) -1.0 - 1.0 VDD= 5 V,  -25°C TA  85 °C -2.0 - 2.0 -3.0(3) - 3.
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Electrical characteristics STM8S105x4/6 Figure 22.
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STM8S105x4/6 Electrical characteristics Low speed internal RC oscillator (LSI) Subject to general operating conditions for VDD and TA. Table 34. LSI oscillator characteristics Symbol Parameter Conditions Min Typ Max Unit fLSI Frequency - 110 128 150 kHz tsu(LSI) LSI oscillator wakeup time - - - 7(1) µs - - 5 - µA IDD(LSI) LSI oscillator power consumption 1. Guaranteed by design, not tested in production. Figure 23.
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Electrical characteristics 10.3.5 STM8S105x4/6 Memory characteristics RAM and hardware registers Table 35. RAM and hardware registers Symbol VRM Parameter Data retention mode(1) Conditions Min Unit Halt mode (or reset) VIT-max(2) V 1. Minimum supply voltage without losing data stored in RAM (in halt mode or under reset) or in hardware registers (only in halt mode). Guaranteed by design, not tested in production. 2. Refer to Section 10.3: Operating conditions for the value of VIT-max.
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STM8S105x4/6 10.3.6 Electrical characteristics I/O port pin characteristics General characteristics Subject to general operating conditions for VDD and TA unless otherwise specified. All unused pins must be kept at a fixed voltage, using the output mode of the I/O for example or an external pull-up or pull-down resistor. Table 37.
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Electrical characteristics STM8S105x4/6 Figure 24. Typical VIL and VIH vs VDD @ 4 temperatures Figure 25. Typical pull-up current vs VDD @ 4 temperatures Figure 26. Typical pull-up resistance vs VDD @ 4 temperatures Û& Û& Û& 3XOO XS UHVLVWDQFH > :@ Û& 9'' >9@ 06 9 Table 38. Output driving current (standard ports) Symbol VOL VOH Parameter Conditions Min Max Output low level with 8 pins sunk IIO= 10 mA, VDD = 5 V - 2.
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STM8S105x4/6 Electrical characteristics Table 39. Output driving current (true open drain ports) Symbol VOL VOH Parameter Conditions Min Max Output low level with 2 pins sunk IIO= 10 mA, VDD = 5 V - 1.0 Output low level with 2 pins sunk IIO= 10 mA, VDD = 3.3 V - 1.5(1) Output high level with 2 pins sourced IIO= 10 mA, VDD = 5 V - 2.0(1) Unit V 1. Data based on characterization results, not tested in production Table 40.
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Electrical characteristics STM8S105x4/6 Figure 29. Typ. VOL @ VDD = 3.3 V (true open drain ports) Figure 30. Typ. VOL @ VDD = 5.0 V (true open drain ports) Figure 31. Typ. VOL @ VDD = 3.3 V (high sink ports) Figure 32. Typ. VOL @ VDD = 5.
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STM8S105x4/6 Electrical characteristics Figure 33. Typ. VDD - VOH @ VDD = 3.3 V (standard ports) Figure 34. Typ. VDD - VOH @ VDD = 5.0 V (standard ports) Figure 35. Typ. VDD - VOH @ VDD = 3.3 V (high sink ports) Figure 36. Typ. VDD - VOH @ VDD = 5.
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Electrical characteristics 10.3.8 STM8S105x4/6 Reset pin characteristics Subject to general operating conditions for VDD and TA unless otherwise specified. Table 41. NRST pin characteristics Symbol Parameter Conditions Min Typ Max VIL(NRST) NRST input low level voltage(1) - -0.3 - 0.3 x VDD VIH(NRST) NRST input high level voltage(1) IOL= 2 mA 0.7 x VDD - VDD+ 0.3 VOL(NRST) NRST output low level voltage(1) IOL= 3 mA - - 0.
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STM8S105x4/6 Electrical characteristics Figure 38. Typical NRST pull-up resistance RPU vs VDD @ 4 temperatures Figure 39. Typical NRST pull-up current Ipu vs VDD @ 4 temperatures The reset network shown in Figure 40 protects the device against parasitic resets. The user must ensure that the level on the NRST pin can go below VIL(NRST) max (see Table 41: NRST pin characteristics), otherwise the reset is not taken into account internally.
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Electrical characteristics STM8S105x4/6 Figure 40. Recommended reset pin protection 670 9'' 538 ([WHUQDO UHVHW FLUFXLW 1567 )LOWHU ȝ) 2SWLRQDO 06Y 9 10.3.9 SPI serial peripheral interface Unless otherwise specified, the parameters given in Table 42 are derived from tests performed under ambient temperature, fMASTER frequency and VDD supply voltage conditions. tMASTER = 1/fMASTER.
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STM8S105x4/6 Electrical characteristics Table 42.
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Electrical characteristics STM8S105x4/6 Figure 41. SPI timing diagram where slave mode and CPHA = 0 166 LQSXW 6&. ,QSXW W68 166 &3+$ &32/ &3+$ &32/ WK 166 WF 6&. WZ 6&.+ WZ 6&./ W9 62 WD 62 0,62 287387 WU 6&. WI 6&. WK 62 06% 287 %,7 287 06% ,1 %,7 ,1 WGLV 62 /6% 287 WVX 6, 026, ,1387 /6% ,1 WK 6, DL F 1. Measurement points are at CMOS levels: 0.3 VDD and 0.7 VDD. Figure 42. SPI timing diagram where slave mode and CPHA = 1 166 LQSXW 6&.
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STM8S105x4/6 Electrical characteristics Figure 43. SPI timing diagram - master mode +LJK 166 LQSXW 6&. 2XWSXW &3+$ &32/ 6&. 2XWSXW WF 6&. &3+$ &32/ &3+$ &32/ &3+$ &32/ WVX 0, 0,62 ,13 87 WZ 6&.+ WZ 6&./ WU 6&. WI 6&. %,7 ,1 06% ,1 /6% ,1 WK 0, 026, 287387 % , 7 287 06% 287 WY 02 /6% 287 WK 02 DL F 1. Measurement points are at CMOS levels: 0.3 VDD and 0.7 VDD.
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Electrical characteristics 10.3.10 STM8S105x4/6 I2C interface characteristics Table 43. I2C characteristics Standard mode I2C Fast mode I2C(1) Symbol Parameter Unit Min(2) Max(2) Min(2) Max(2) tw(SCLL) SCL clock low time 4.7 - 1.3 - tw(SCLH) SCL clock high time 4.0 - 0.6 - tsu(SDA) SDA setup time 250 - 100 - th(SDA) SDA data hold time 0(3) - 0(4) 900(3) tr(SDA) tr(SCL) SDA and SCL rise time (VDD = 3 to 5.
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STM8S105x4/6 10.3.11 Electrical characteristics 10-bit ADC characteristics Subject to general operating conditions for VDDA, fMASTER, and TA unless otherwise specified. Table 44. ADC characteristics Symbol Parameter Conditions Min Typ Max VDD= 2.95 to 5.5 V 1 - 4 VDD= 4.5 to 5.5 V 1 - 6 fADC ADC clock frequency VDDA Analog supply - 3.0 - 5.5 VREF+ Positive reference voltage - 2.75(1) - VDDA VREF- Negative reference voltage - VSSA - 0.
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Electrical characteristics STM8S105x4/6 Table 45. ADC accuracy with RAIN< 10 k, VDDA = 5 V Symbol |ET| |EO| |EG| |ED| |EL| Parameter Total unadjusted Offset Gain error(2) error(2) error(2) Differential linearity Integral linearity error(2) error(2) Conditions Typ Max(1) fADC = 2 MHz 1.0 2.5 fADC = 4 MHz 1.4 3.0 fADC = 6 MHz 1.6 3.5 fADC = 2 MHz 0.6 2.0 fADC = 4 MHz 1.1 2.5 fADC = 6 MHz 1.2 2.5 fADC = 2 MHz 0.2 2.0 fADC = 4 MHz 0.6 2.5 fADC = 6 MHz 0.8 2.
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STM8S105x4/6 Electrical characteristics 2. ADC accuracy vs. negative injection current: Injecting negative current on any of the analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to standard analog pins which may potentially inject negative current. Any positive injection current within the limits specified for IINJ(PIN) and IINJ(PIN) in Section 10.3.
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Electrical characteristics 10.3.12 STM8S105x4/6 EMC characteristics Susceptibility tests are performed on a sample basis during product characterization. Functional EMS (electromagnetic susceptibility) While executing a simple application (toggling 2 LEDs through I/O ports), the product is stressed by two electromagnetic events until a failure occurs (indicated by the LEDs).
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STM8S105x4/6 Electrical characteristics 1. Data obtained with HSI clock configuration, after applying the hardware recommendations described in AN2860 (EMC guidelines for STM8S microcontrollers). Electromagnetic interference (EMI) Based on a simple application running on the product (toggling 2 LEDs through the I/O ports), the product is monitored in terms of emission. This emission test is in line with the norm IEC 61967-2 which specifies the board and the loading of each pin. Table 48.
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Electrical characteristics STM8S105x4/6 Static latch-up Two complementary static tests are required on 10 parts to assess the latch-up performance.  A supply overvoltage (applied to each power supply pin), and  A current injection (applied to each input, output and configurable I/O pin) are performed on each sample. This test conforms to the EIA/JESD 78 IC latch-up standard. For more details, refer to the application note AN1181. Table 50.
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STM8S105x4/6 11 Package information Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. LQFP48 package information Figure 47. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package outline 3%!4).' 0,!.% # C ! ! ! MM '!5'% 0,!.
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Package information STM8S105x4/6 Table 51. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A - - 1.600 - - 0.0630 A1 0.050 - 0.150 0.0020 - 0.0059 A2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 D 8.800 9.000 9.200 0.3465 0.3543 0.3622 D1 6.800 7.000 7.200 0.2677 0.2756 0.2835 D3 - 5.500 - - 0.
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STM8S105x4/6 Package information Figure 48. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package recommended footprint AI D 1. Dimensions are expressed in millimeters. Device marking The following figure gives an example of topside marking orientation versus pin 1 identifier location. Figure 49. LQFP48 marking example (package top view) 3URGXFW LGHQWLILFDWLRQ 45.
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Package information STM8S105x4/6 usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering samples in production. ST Quality has to be contacted prior to any decision to use these Engineering Samples to run qualification activity. 11.2 LQFP44 package information Figure 50. LQFP44 - 44-pin, 10 x 10 mm low-profile quad flat package outline 3%!4).' 0,!.% ! ! ! # MM '!5'% 0,!.% # ! CCC + , $ , $ $ 0). )$%.4)&)#!4)/.
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STM8S105x4/6 Package information Table 52. LQFP44 - 44-pin, 10 x 10 mm low-profile quad flat package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A - - 1.600 - - 0.0630 A1 0.050 - 0.150 0.0020 - 0.0059 A2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.300 0.370 0.450 0.0118 0.0146 0.0177 c 0.090 - 0.200 0.0035 - 0.0079 D 11.800 12.000 12.200 0.4646 0.4724 0.4803 D1 9.800 10.000 10.200 0.3858 0.3937 0.4016 D3 - 8.000 - - 0.
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Package information STM8S105x4/6 Figure 51. LQFP44 - 44-pin, 10 x 10 mm low-profile quad flat package recommended footprint
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STM8S105x4/6 Package information Figure 52. LQFP44 marking example (package top view) 3URGXFW LGHQWLILFDWLRQ 45. 4 4 5 $ 'DWH FRGH 6WDQGDUG 67 ORJR : 88 5HYLVLRQ FRGH 3LQ LGHQWLILHU 3 06 9 1. Parts marked as "ES", "E" or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge.
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Package information 11.3 STM8S105x4/6 LQFP32 package information Figure 53. LQFP32 - 32-pin, 7 x 7 mm low-profile quad flat package outline C ! ! ! 3%!4).' 0,!.% # MM CCC '!5'% 0,!.% # + $ ! , $ , $ 0). )$%.4)&)#!4)/. % E 1. Drawing is not to scale. 98/121 % % B DocID14771 Rev 15 7@.
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STM8S105x4/6 Package information Table 53. LQFP32 - 32-pin, 7 x 7 mm low-profile quad flat package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A - - 1.600 - - 0.0630 A1 0.050 - 0.150 0.0020 - 0.0059 A2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.300 0.370 0.450 0.0118 0.0146 0.0177 c 0.090 - 0.200 0.0035 - 0.0079 D 8.800 9.000 9.200 0.3465 0.3543 0.3622 D1 6.800 7.000 7.200 0.2677 0.2756 0.2835 D3 - 5.600 - - 0.
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Package information STM8S105x4/6 Figure 54. LQFP32 - 32-pin, 7 x 7 mm low-profile quad flat package recommended footprint 6?&0?6 1. Dimensions are expressed in millimeters. Device marking The following figure gives an example of topside marking orientation versus pin 1 identifier location. Figure 55. LQFP32 marking example (package top view) 3URGXFW LGHQWLILFDWLRQ 45.
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STM8S105x4/6 11.4 Package information UFQFPN32 package information Figure 56. UFQFPN32 - 32-pin, 5x5 mm, 0.5 mm pitch ultra thin fine pitch quad flat package outline ' $ H ' $ $ GGG & & 6($7,1* 3/$1( E H ( E ( ( / 3,1 ,GHQWLILHU ' / ! " ?-%?6 1. Drawing is not to scale. 2. All leads/pads should be soldered to the PCB to improve the lead/pad solder joint life. 3. There is an exposed die pad on the underside of the UFQFPN package.
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Package information STM8S105x4/6 Table 54. UFQFPN32 - 32-pin, 5x5 mm, 0.5 mm pitch ultra thin fine pitch quad flat package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A 0.500 0.550 0.600 0.0197 0.0217 0.0236 A1 0.000 0.020 0.050 0.0000 0.0008 0.0020 A3 - 0.152 - - 0.0060 - b 0.180 0.230 0.280 0.0071 0.0091 0.0110 D 4.900 5.000 5.100 0.1929 0.1969 0.2008 D1 3.400 3.500 3.600 0.1339 0.1378 0.1417 D2 3.400 3.500 3.600 0.1339 0.
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STM8S105x4/6 Package information Device marking The following figure gives an example of topside marking orientation versus pin 1 identifier location. Figure 58. UFQFPN32 marking example (package top view) 3URGXFW LGHQWLILFDWLRQ 4 , 'DWH FRGH : 88 6WDQGDUG 67 ORJR 5HYLVLRQ FRGH 3 3LQ LGHQWLILHU 06 9 1.
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Package information 11.5 STM8S105x4/6 SDIP32 package information Figure 59. SDIP32 package outline % % ! ! " " ! , E E! # E" $ ?-% Table 55. SDIP32 package mechanical data inches(1) mm Dim. 104/121 Min Typ Max Min Typ Max A 3.556 3.759 5.080 0.1400 0.1480 0.2000 A1 0.508 - - 0.0200 - - A2 3.048 3.556 4.572 0.1200 0.1400 0.1800 B 0.356 0.457 0.584 0.0140 0.0180 0.0230 B1 0.762 1.016 1.397 0.0300 0.0400 0.0550 C 0.203 0.254 0.
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STM8S105x4/6 Package information Table 55. SDIP32 package mechanical data (continued) inches(1) mm Dim. Min Typ Max Min Typ Max eB - - 12.700 - - 0.5000 L 2.540 3.048 3.810 0.1000 0.1200 0.1500 1. Values in inches are converted from mm and rounded to 4 decimal digits Device marking The following figure gives an example of topside marking orientation versus pin 1 identifier location. Figure 60. SDIP32 marking example (package top view) 3URGXFW LGHQWLILFDWLRQ 5HYLVLRQ FRGH 45.
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Thermal characteristics 12 STM8S105x4/6 Thermal characteristics The maximum junction temperature (TJmax) of the device must never exceed the values specified in Table 18: General operating conditions, otherwise the functionality of the device cannot be guaranteed.
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STM8S105x4/6 12.2 Thermal characteristics Selecting the product temperature range When ordering the microcontroller, the temperature range is specified in the order code (see Section 13: Ordering information). The following example shows how to calculate the temperature range needed for a given application. Assuming the following application conditions: Maximum ambient temperature TAmax= 82°C (measured according to JESD51-2), IDDmax = 15 mA, VDD = 5.
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Ordering information 13 STM8S105x4/6 Ordering information Figure 61. STM8S105x4/6 access line ordering information scheme(1) STM8 Example: S 105 K 4 T 6 TR Product class STM8 microcontroller Family type S = Standard Sub-family type 10x = Access line 105 sub-family Pin count K = 32 pins S = 44 pins C = 48 pins Program memory size 4 = 16 Kbyte 6 = 32 Kbyte Package type B = SDIP T = LQFP U = UFQFPN Temperature range 3 = -40 to 125 °C 6 = -40 to 85 °C Package pitch/thickness Blank = 0.5 mm C = 0.
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STM8S105x4/6 13.1 Ordering information STM8S105 FASTROM microcontroller option list (last update: September 2010) Customer ............................................................................... Address ............................................................................... Contact ............................................................................... Phone number ............................................................................... FASTROM code reference(1) ..
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Ordering information STM8S105x4/6 Padding value for unused program memory (check only one option) [ ] 0xFF Fixed value [ ] 0x83 TRAP instruction code [ ] 0x75 Illegal opcode (causes a reset when executed) OTP0 memory readout protection (check only one option) [ ] Disable or [ ] Enable OTP1 user boot code area (UBC) 0x(_ _) fill in the hexadecimal value, referring to the datasheet and the binary format below: UBC, bit0 [ ] 0: Reset [ ] 1: Set UBC, bit1 [ ] 0: Reset [ ] 1: Set UBC, bit2 [ ] 0:
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STM8S105x4/6 Ordering information AFR4 (check only one option) [ ] 0: Remapping option inactive. Default alternate functions used. Refer to pinout description [ ] 1: Port D7 alternate function = TIM1_CH4 AFR5 (check only one option) [ ] 0: Remapping option inactive. Default alternate functions used. Refer to pinout description [ ] 1: Port B3 alternate function = TIM1_ETR, port B2 alternate function = TIM1_NCC3, port B1 alternate function = TIM1_CH2N, port B0 alternate function = TIM1_CH1N.
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Ordering information STM8S105x4/6 OPT5 crystal oscillator stabilization HSECNT (check only one option) [ ] 2048 HSE cycles [ ] 128 HSE cycles [ ] 8 HSE cycles [ ] 0.5 HSE cycles OTP6 is reserved OTP7 is reserved OTPBL bootloader option byte (check only one option) Refer to the UM0560 (STM8L/S bootloader manual) for more details. [ ] Disable (00h) [ ] Enable (55h) Comments: .........................................................................................
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STM8S105x4/6 14 STM8 development tools STM8 development tools Development tools for the STM8 microcontrollers include the full-featured STice emulation system supported by a complete software tool package including C compiler, assembler and integrated development environment with high-level language debugger. In addition, the STM8 is to be supported by a complete range of tools including starter kits, evaluation boards and a low-cost in-circuit debugger/programmer. 14.
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STM8 development tools 14.2 STM8S105x4/6 Software tools STM8 development tools are supported by a complete, free software package from STMicroelectronics that includes ST Visual Develop (STVD) IDE and the ST Visual Programmer (STVP) software interface. STVD provides seamless integration of the Cosmic and Raisonance C compilers for STM8, which are available in a free version that outputs up to 16 Kbytes of code. 14.2.
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STM8S105x4/6 14.3 STM8 development tools Programming tools During the development cycle, STice provides in-circuit programming of the STM8 Flash microcontroller on the application board via the SWIM protocol. Additional tools include a low-cost in-circuit programmer as well as ST socket boards, which provide dedicated programming platforms with sockets for the STM8 programming.
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Revision history 15 STM8S105x4/6 Revision history Table 57. Document revision history Date Revision 05-Jun-2018 1 Initial release. 2 Corrected the number of high sink outputs to 9 in I/Os in Features. Updated part numbers in STM8S105xx access line features. 3 Updated the part numbers in STM8S105xx access line features. USART renamed UART1, LINUART renamed UART2. Added Table: Pin-to-pin comparison of pin 7 to 12 in 32pin access line devices.
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STM8S105x4/6 Revision history Table 57. Document revision history (continued) Date 12-May-2009 10-Jun-2009 Revision Changes 7 Added SDIP32 silhouette and package to Features and Section: SDIP32 package mechanical data; updated Section: Pinout and pin description. Updated VDD range (2.95 V to 5.5 V) on Features. Amended name of package VQFPN32. Added Table 5 on page 22. Updated Section: Auto wakeup counter. Updated pins 25, 30, and 31 in Section: Pinout and pin description.
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Revision history STM8S105x4/6 Table 57. Document revision history (continued) Date 21-Apr-2010 118/121 Revision Changes 9 Added UFQFPN32 package silhouette to the title page. In Features: added unique ID. Section: Clock controller: updated bit positions for TIM2 and TIM3. Section: Beeper: added information about availability of the beeper output port through option bit AFR7. Section: Analog-to-digital converter (ADC1): added a note concerning additional AIN12 analog input.
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STM8S105x4/6 Revision history Table 57. Document revision history (continued) Date Revision Changes 10 Table: Legend/Abbreviations for pinout tables: updated "reset state"; removed "HS", (T), and "[ ]". Section: Pin description for STM8S105 microcontrollers: added footnotes to the PF4 and PD1 pins. Table: I/O port hardware register map: changed reset status of Px_IDR from 0x00 to 0xXX.
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Revision history STM8S105x4/6 Table 57. Document revision history (continued) Date Revision Changes 13 UART2_CK mapped to correct pin (pin 24) in Figure: LQFP 44-pin pinout. Reserved area updated in Table: Option bytes. Package Information updated in Table: 32-lead ultra thin fine pitch quad flat no-lead package mechanical data.
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STM8S105x4/6 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.