Datasheet

Electrical characteristics
STM8S105xx
Prequalification trials
Most of the common failures (unexpected reset and program counter corruption) can be
recovered by applying a low state on the NRST pin or the oscillator pins for 1 second.
To complete these trials, ESD stress can be applied directly on the device, over the range
of specification values. When unexpected behavior is detected, the software can be
hardened to prevent unrecoverable errors occurring. See application note AN1015
(Software techniques for improving microcontroller EMC performance).
Table 48: EMS data
Symbol
Parameter Conditions Level/
class
V
FESD
Voltage limits to be applied on any I/O
pin to induce a functional disturbance
V
DD
= 3.3 V, T
A
= 25 °C, f
MASTER
=
16 MHz (HSI clock), conforming to
IEC 61000-4-2
V
DD
= 5 V, T
A
= 25 °C, f
MASTER
= 16
MHz, conforming to IEC 1000-4-2
2/B
(1)
V
EFTB
Fast transient voltage burst limits to be
applied through 100 pF on V
DD
and V
SS
pins to induce a functional disturbance
V
DD
= 3.3 V, T
A
= 25 °C ,f
MASTER
= 16
MHz (HSI clock),conforming to IEC
61000-4-4
V
DD
= 5 V, T
A
= 25 °C ,f
MASTER
= 16
MHz,conforming to IEC 1000-4-4
4/A
(1)
Notes:
(1)
Data obtained with HSI clock configuration, after applying HW recommendations described in AN2860 (EMC
guidelines for STM8S microcontrollers).
10.3.12.3 Electromagnetic interference (EMI)
Emission tests conform to the IEC61967-2 standard for test software, board layout and pin
loading.
Table 49: EMI data
Symbol Parameter Conditions Unit
General conditions Monitored
frequency band
Max f
HSE
/f
CPU
(1)
8 MHz/
8 MHz
8 MHz/
16 MHz
S
EMI
Peak level V
DD
= 5 V,
T
A
= +25 °C,
LQFP48 package
conforming to
IEC61967-2
0.1 MHz to 30
MHz
13 14 dBµV
30 MHz to 130
MHz
23 19
130 MHz to 1
GHz
-4.0 -4.0
SAE EMI
level
2.0 1.5 —
Notes:
(1)
Data based on characterization results, not tested in production.
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