Datasheet

Electrical characteristics
STM8S105xx
Symbol Parameter Standard mode I
2
C Fast mode I
2
C
(1)
Unit
Min
(2)
Max
(2)
Min
(2)
Max
(2)
C
b
Capacitive load for each bus line 400 400 pF
Notes:
(1)
f
MASTER
, must be at least 8 MHz to achieve max fast I
2
C speed (400kHz).
(2)
Data based on standard I
2
C protocol requirement, not tested in production.
(3)
The maximum hold time of the start condition has only to be met if the interface does not stretch the low time.
(4)
The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the
undefined region of the falling edge of SCL.
Figure 44: Typical application with I2C bus and timing diagram (1)
1. Measurement points are made at CMOS levels: 0.3 x V
DD
and 0.7 x V
DD
10.3.11 10-bit ADC characteristics
Subject to general operating conditions for V
DDA
, f
MASTER
, and T
A
unless otherwise specified.
Table 45: ADC characteristics
Symbol Parameter Conditions Min Typ Max Unit
f
ADC
ADC clock frequency V
DDA
=2.95 to 5.5 V 1.0 4.0 MHz
V
DDA
=4.5 to 5.5 V 1.0 6.0
V
DDA
Analog supply 3.0 5.5 V
V
REF+
Positive reference voltage 2.75
(1)
V
DDA
V
V
REF-
Negative reference voltage
VSSA
0.5 V
74/99 DocID14771 Rev 13