Datasheet

STM8S105xx
Electrical characteristics
Figure 43: SPI timing diagram - master mode(1)
1. Measurement points are made at CMOS levels: 0.3 V
DD
and 0.7 V
DD
.
10.3.10 I2C interface characteristics
Table 44: I2C characteristics
Symbol Parameter Standard mode I
2
C Fast mode I
2
C
(1)
Unit
Min
(2)
Max
(2)
Min
(2)
Max
(2)
t
w(SCLL)
SCL clock low time 4.7 1.3 μs
t
w(SCLH)
SCL clock high time 4.0 0.6 μs
t
su(SDA)
SDA setup time 250 100 ns
t
h(SDA)
SDA data hold time 0
(3)
0
(4)
900
(3)
ns
t
r(SDA)
t
r(SCL)
SDA and SCL rise time
1000 300 ns
t
f(SDA)
t
f(SCL)
SDA and SCL fall time 300 300 ns
t
h(STA)
START condition hold time 4.0 0.6 μs
t
su(STA)
Repeated START condition
setup time
4.7 0.6 μs
t
su(STO)
STOP condition setup time 4.0 0.6 μs
t
w(STO:STA)
STOP to START condition time
(bus free)
4.7 1.3 μs
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