Datasheet

STM8S105xx
Electrical characteristics
Table 43: SPI characteristics
Symbol Parameter Conditions Min Max Unit
f
SCK
1
t
c(SCK)
SPI clock frequency Master mode 0 8
MHz
Slave mode 0 6
t
r(SCK)
t
f(SCK)
SPI clock rise and fall
time
Capacitive load: C = 30
pF
25 ns
t
su(NSS)
(1)
NSS setup time Slave mode 4 x
t
MASTER
ns
t
h(NSS)
(1)
NSS hold time Slave mode 70 ns
t
w(SCKH)
(1)
t
w(SCKL)
(1)
SCK high and low time Master mode t
SCK
/2 - 15 t
SCK
/2 +
15
ns
t
su(MI)
(1)
t
su(SI)
(1)
Data input setup time Master mode 5 ns
Data input setup time Slave mode 5 ns
t
h(MI)
(1)
t
h(SI)
(1)
Data input hold time Master mode 7
ns
Data input hold time Slave mode 10 ns
t
a(SO)
(1)(2)
Data output access time Slave mode 3 x t
MASTER
ns
t
dis(SO)
(1)(3)
Data output disable time Slave mode 25 ns
t
v(SO)
(1)
Data output valid time Slave mode
(after enable edge)
73 ns
t
v(MO)
(1)
Data output valid time Master mode
(after enable edge)
36 ns
t
h(SO)
(1)
Data output hold time Slave mode
(after enable edge)
28 ns
t
h(MO)
(1)
Master mode
(after enable edge)
12 ns
Notes:
(1)
Values based on design simulation and/or characterization results, and not tested in production.
(2)
Min time is for the minimum time to drive the output and the max time is for the maximum time to validate the
data.
(3)
Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the
data in Hi-Z.
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