Datasheet

STM8S105xx
List of figures
List of figures
Figure 1: STM8S105xx access line block diagram ................................................................................... 10
Figure 2: Flash memory organization ....................................................................................................... 13
Figure 3: LQFP 48-pin pinout ................................................................................................................... 19
Figure 4: LQFP 44-pin pinout ................................................................................................................... 20
Figure 5: LQFP/UFQFPN 32-pin pinout .................................................................................................... 21
Figure 6: SDIP 32-pin pinout .................................................................................................................... 21
Figure 7: Memory map .............................................................................................................................. 25
Figure 8: Supply current measurement conditions ................................................................................... 42
Figure 9: Pin loading conditions ................................................................................................................ 43
Figure 10: Pin input voltage ...................................................................................................................... 43
Figure 11: fCPUmax versus VDD ............................................................................................................. 46
Figure 12: External capacitor CEXT ......................................................................................................... 47
Figure 13: Typ. IDD(RUN) vs. VDD, HSE user external clock, fCPU = 16 MHz ...................................... 54
Figure 14: Typ. IDD(RUN) vs. fCPU, HSE user external clock, VDD= 5 V .............................................. 54
Figure 15: Typ. IDD(RUN) vs. VDD, HSI RC osc, fCPU = 16 MHz .......................................................... 54
Figure 16: Typ. IDD(WFI) vs. VDD, HSE user external clock, fCPU = 16 MHz ....................................... 55
Figure 17: Typ. IDD(WFI) vs. fCPU, HSE user external clock VDD = 5 V ............................................... 55
Figure 18: Typ. IDD(WFI) vs. VDD, HSI RC osc, fCPU = 16 MHz ........................................................... 55
Figure 19: HSE external clocksource ....................................................................................................... 56
Figure 20: HSE oscillator circuit diagram.................................................................................................. 57
Figure 21: Typical HSI accuracy at VDD = 5 V vs 5 temperatures ........................................................... 58
Figure 22: Typical HSI accuracy vs VDD @ 4 temperatures ................................................................... 59
Figure 23: Typical LSI accuracy vs VDD @ 4 temperatures .................................................................... 59
Figure 24: Typical VIL and VIH vs VDD @ 4 temperatures ..................................................................... 62
Figure 25: Typical pull-up resistance vs VDD @ 4 temperatures ............................................................. 62
Figure 26: Typical pull-up current vs VDD @ 4 temperatures .................................................................. 63
Figure 27: Typ. VOL @ VDD = 5 V (standard ports) ................................................................................ 64
Figure 28: Typ. VOL @ VDD = 3.3 V (standard ports) ............................................................................. 65
Figure 29: Typ. VOL @ VDD = 5 V (true open drain ports) ...................................................................... 65
Figure 30: Typ. VOL @ VDD = 3.3 V (true open drain ports) ................................................................... 66
Figure 31: Typ. VOL @ VDD = 5 V (high sink ports) ................................................................................ 66
Figure 32: Typ. VOL @ VDD = 3.3 V (high sink ports) ............................................................................. 67
Figure 33: Typ. VDD - VOH @ VDD = 5 V (standard ports) ..................................................................... 67
Figure 34: Typ. VDD - VOH @ VDD = 3.3 V (standard ports) .................................................................. 67
Figure 35: Typ. VDD - VOH @ VDD = 5 V (high sink ports) .................................................................... 68
Figure 36: Typ. VDD - VOH @ VDD = 3.3 V (high sink ports) ................................................................. 68
Figure 37: Typical NRST VIL and VIH vs VDD @ 4 temperatures ........................................................... 69
Figure 38: Typical NRST pull-up resistance vs VDD @ 4 temperatures .................................................. 69
Figure 39: Typical NRST pull-up current vs VDD @ 4 temperatures ....................................................... 70
Figure 40: Recommended reset pin protection ........................................................................................ 70
Figure 41: SPI timing diagram - slave mode and CPHA = 0 .................................................................... 72
Figure 42: SPI timing diagram - slave mode and CPHA = 1(1) ................................................................ 72
Figure 43: SPI timing diagram - master mode(1) ..................................................................................... 73
Figure 44: Typical application with I2C bus and timing diagram (1) ......................................................... 74
Figure 45: ADC accuracy characteristics .................................................................................................. 76
Figure 46: Typical application with ADC ................................................................................................... 77
Figure 47: 48-pin low profile quad flat package (7 x 7) ............................................................................. 80
Figure 48: 44-pin low profile quad flat package ........................................................................................ 81
Figure 49: 32-pin low profile quad flat package (7 x 7) ............................................................................. 82
Figure 50: 32-lead, ultra thin, fine pitch quad flat no-lead package (5 x 5) .............................................. 84
Figure 51: 32-lead shrink plastic DIP (400 ml) package ........................................................................... 85
Figure 52: STM8S105xx access line ordering information scheme ......................................................... 89
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