Datasheet
STM8S105xx
Electrical characteristics
(6)
Plus 1 LSI clock depending on synchronization.
10.3.2.6 Total current consumption and timing in forced reset state
Table 30: Total current consumption and timing in forced reset state
Symbol Parameter Conditions Typ Max
(1)
Unit
I
DD(R)
Supply current in reset state
(2)
V
DD
= 5 V 500
μA
V
DD
= 3.3 V 400
t
RESETBL
Reset pin release to vector fetch
150 μs
Notes:
(1)
Data guaranteed by design, not tested in production.
(2)
Characterized with all I/Os tied to V
SS
.
10.3.2.7 Current consumption of on-chip peripherals
Subject to general operating conditions for V
DD
and T
A
.
HSI internal RC/f
CPU
= f
MASTER
= 16 MHz.
Table 31: Peripheral current consumption
Symbol Parameter Typ. Unit
I
DD(TIM1)
TIM1 supply current
(1)
230 µA
I
DD(TIM2)
TIM2 supply current
(1)
115
I
DD(TIM3)
TIM3 timer supply current
(1)
90
I
DD(TIM4)
TIM4 timer supply current
(1)
30
I
DD(UART2)
UART2 supply current
(2)
110
I
DD(SPI)
SPI supply current
(2)
45
I
DD(I
2
C)
I
2
C supply current
(2)
65
I
DD(ADC1)
ADC1 supply current when converting
(3)
955
Notes:
(1)
Data based on a differential I
DD
measurement between reset configuration and timer counter running at 16
MHz. No IC/OC programmed (no I/O pads toggling). Not tested in production.
(2)
Data based on a differential I
DD
measurement between the on-chip peripheral when kept under reset and not
clocked and the on-chip peripheral when clocked and not kept under reset. No I/O pads toggling. Not tested in
production.
(3)
Data based on a differential I
DD
measurement between reset configuration and continuous A/D conversions.
Not tested in production.
10.3.2.8 Current consumption curves
The following figures show typical current consumption measured with code executing in
RAM.
DocID14771 Rev 13 53/99