Datasheet

STM8S105xx
Memory and register map
Address Block Register label Register name Reset
status
0x00 5342 TIM4_SR TIM4 status register 0x00
0x00 5343 TIM4_EGR TIM4 event generation register 0x00
0x00 5344 TIM4_CNTR TIM4 counter 0x00
0x00 5345 TIM4_PSCR TIM4 prescaler register 0x00
0x00 5346 TIM4_ARR TIM4 auto-reload register 0xFF
0x00 5347 to
0x00 53DF
Reserved area (153 bytes)
0x00 53E0 to
0x00 53F3
ADC1 ADC _DBxR ADC data buffer registers 0x00
0x00 53F4 to
0x00 53FF
Reserved area (12 bytes)
0x00 5400 ADC1 ADC _CSR ADC control/ status register 0x00
0x00 5401 ADC_CR1 ADC configuration register 1 0x00
0x00 5402 ADC_CR2 ADC configuration register 2 0x00
0x00 5403 ADC_CR3 ADC configuration register 3 0x00
0x00 5404 ADC_DRH ADC data register high 0xXX
0x00 5405 ADC_DRL ADC data register low 0xXX
0x00 5406 ADC_TDRH ADC Schmitt trigger disable
register high
0x00
0x00 5407 ADC_TDRL ADC Schmitt trigger disable
register low
0x00
0x00 5408 ADC_HTRH ADC high threshold register high 0x03
0x00 5409 ADC_HTRL ADC high threshold register low 0xFF
0x00 540A ADC_LTRH ADC low threshold register high 0x00
0x00 540B ADC_LTRL ADC low threshold register low 0x00
0x00 540C ADC_AWSRH ADC analog watchdog status
register high
0x00
0x00 540D ADC_AWSRL ADC analog watchdog status
register low
0x00
0x00 540E ADC _AWCRH ADC analog watchdog control
register high
0x00
0x00 540F ADC_AWCRL ADC analog watchdog control
register low
0x00
0x00 5410 to
0x00 57FF
Reserved area (1008 bytes)
Notes:
(1)
Depends on the previous reset source.
(2)
Write only register.
DocID14771 Rev 13 33/99