Datasheet

Memory and register map
STM8S105xx
Address Block Register label Register name Reset
status
0x00 530F TIM2_CCR1H TIM2 capture/ compare register 1
high
0x00
0x00 5310 TIM2_CCR1L TIM2 capture/ compare register 1
low
0x00
0x00 5311 TIM2_CCR2H TIM2 capture/ compare reg. 2 high 0x00
0x00 5312 TIM2_CCR2L TIM2 capture/ compare register 2
low
0x00
0x00 5313 TIM2_CCR3H TIM2 capture/ compare register 3
high
0x00
0x00 5314 TIM2_CCR3L TIM2 capture/ compare register 3
low
0x00
0x00 5315 to
0x00 531F
Reserved area (11 bytes)
0x00 5320 TIM3 TIM3_CR1 TIM3 control register 1 0x00
0x00 5321 TIM3_IER TIM3 interrupt enable register 0x00
0x00 5322 TIM3_SR1 TIM3 status register 1 0x00
0x00 5323 TIM3_SR2 TIM3 status register 2 0x00
0x00 5324 TIM3_EGR TIM3 event generation register 0x00
0x00 5325 TIM3_CCMR1 TIM3 capture/ compare mode
register 1
0x00
0x00 5326 TIM3_CCMR2 TIM3 capture/ compare mode
register 2
0x00
0x00 5327 TIM3_CCER1 TIM3 capture/ compare enable
register 1
0x00
0x00 5328 TIM3_CNTRH TIM3 counter high 0x00
0x00 5329 TIM3_CNTRL TIM3 counter low 0x00
0x00 532A TIM3_PSCR TIM3 prescaler register 0x00
0x00 532B TIM3_ARRH TIM3 auto-reload register high 0xFF
0x00 532C TIM3_ARRL TIM3 auto-reload register low 0xFF
0x00 532D TIM3_CCR1H TIM3 capture/ compare register 1
high
0x00
0x00 532E TIM3_CCR1L TIM3 capture/ compare register 1
low
0x00
0x00 532F TIM3_CCR2H TIM3 capture/ compare register 2
high
0x00
0x00 5330 TIM3_CCR2L TIM3 capture/ compare register 2
low
0x00
0x00 5331 to
0x00 533F
Reserved area (15 bytes)
0x00 5340 TIM4 TIM4_CR1 TIM4 control register 1 0x00
0x00 5341 TIM4_IER TIM4 interrupt enable register 0x00
32/99 DocID14771 Rev 13