Datasheet

Memory and register map
STM8S105xx
Address Block Register label Register name Reset
status
0x00 5063 Reserved area (1 byte)
0x00 5064 Flash FLASH _DUKR Data EEPROM unprotection
register
0x00
0x00 5065 to
0x00 509F
Reserved area (59 bytes)
0x00 50A0 ITC EXTI_CR1 External interrupt control register 1 0x00
0x00 50A1 EXTI_CR2 External interrupt control register 2 0x00
0x00 50A2 to
0x00 50B2
Reserved area (17 bytes)
0x00 50B3 RST RST_SR Reset status register 0xXX
(1)
0x00 50B4 to
0x00 50BF
Reserved area (12 bytes)
0x00 50C0 CLK CLK_ICKR Internal clock control register 0x01
0x00 50C1 CLK_ECKR External clock control register 0x00
0x00 50C2 Reserved area (1 byte)
0x00 50C3 CLK CLK_CMSR Clock master status register 0xE1
0x00 50C4 CLK_SWR Clock master switch register 0xE1
0x00 50C5 CLK_SWCR Clock switch control register 0xXX
0x00 50C6 CLK_CKDIVR Clock divider register 0x18
0x00 50C7 CLK_PCKENR1 Peripheral clock gating register 1 0xFF
0x00 50C8 CLK_CSSR Clock security system register 0x00
0x00 50C9 CLK_CCOR Configurable clock control register 0x00
0x00 50CA CLK_PCKENR2 Peripheral clock gating register 2 0xFF
0x00 50CB CLK_CANCCR CAN clock control register 0x00
0x00 50CC CLK_HSITRIMR HSI clock calibration trimming
register
0x00
0x00 50CD CLK_SWIMCCR SWIM clock control register 0bXXXX
XXX0
0x00 50CE to
0x00 50D0
Reserved area (3 bytes)
0x00 50D1 WWDG WWDG_CR WWDG control register 0x7F
0x00 50D2 WWDG_WR WWDR window register 0x7F
0x00 50D3 to
0x00 50DF
Reserved area (13 bytes)
0x00 50E0 IWDG IWDG_KR IWDG key register 0xXX
(2)
0x00 50E1 IWDG_PR IWDG prescaler register 0x00
0x00 50E2 IWDG_RLR IWDG reload register 0xFF
0x00 50E3 to
0x00 50EF
Reserved area (13 bytes)
0x00 50F0 AWU AWU_CSR1 AWU control/ status register 1 0x00
28/99 DocID14771 Rev 13