Datasheet
STM8S105xx
Pinout and pin description
Pin number
Pin name
Type
Input
Output
Main
function
(after
reset)
Default alternate
function
Alternate function
after remap
[option bit]
LQFP48
LQFP44
LQFP32/
UFQFPN32
SDIP32
floating
wpu
Ext. interrupt
High sink
Speed
OD
PP
27
25
19
24
PC2/ TIM1_CH2
I/O
X
X
X
HS
O3
X
X
Port C2
Timer 1- channel 2
28
26
20
25
PC3/ TIM1_CH3
I/O
X
X
X
HS
O3
X
X
Port C3
Timer 1 - channel 3
29
-
21
26
PC4/ TIM1_CH4
I/O
X
X
X
HS
O3
X
Port C4
Timer 1 - channel 4
30
27
22
27
PC5/ SPI_SCK
I/O
X
X
X
HS
O3
X
X
Port C5
SPI clock
31
28
-
-
V
SSIO_2
S
I/O ground
32
29
-
-
V
DDIO_2
S
I/O power supply
33
30
23
28
PC6/ SPI_MOSI
I/O
X
X
X
HS
O3
X
X
Port C6
SPI master out/slave in
34
31
24
29
PC7/ SPI_MISO
I/O
X
X
X
HS
O3
X
X
Port C7
SPI master in/ slave out
35
32
-
-
PG0
I/O
X
X
O1
X
X
Port G0
36
33
-
-
PG1
I/O
X
X
O1
X
X
Port G1
37
-
-
-
PE3/ TIM1_BKIN
I/O
X
X
X
O1
X
X
Port E3
Timer 1 - break input
38
34
-
-
PE2/ I
2
C_SDA
I/O
X
X
O1
T
(4)
Port E2
I
2
C data
39
35
-
-
PE1/ I
2
C_ SCL
I/O
X
X
O1
T
(4)
Port E1
I
2
C clock
40
36
-
-
PE0/ CLK_ CCO
I/O
X
X
X
HS
O3
X
X
Port E0
Configurable clock
output
41
37
25
30
PD0/ TIM3_CH2
[TIM1_BKIN]
[CLK_CCO]
I/O
X
X
X
HS
O3
X
X
Port D0
Timer 3 - channel 2
TIM1_BKIN [AFR3]/
CLK_CCO [AFR2]
42
38
26
31
PD1/ SWIM
(5)
I/O
X
X
X
HS
O4
X
X
Port D1
SWIM data interface
43
39
27
32
PD2/ TIM3_CH1
[TIM2_CH3]
I/O
X
X
X
HS
O3
X
X
Port D2
Timer 3 - channel 1
TIM2_CH3 [AFR1]
44
40
28
1
PD3/
TIM2_CH2
[ADC_ETR]
I/O
X
X
X
HS
O3
X
X
Port D3
Timer 2 - channel 2
ADC_ETR [AFR0]
45
41
29
2
PD4/
TIM2_CH1
[BEEP]
I/O
X
X
X
HS
O3
X
X
Port D4
Timer 2 - channel 1
BEEP output [AFR7]
46
42
30
3
PD5/
UART2_TX
I/O
X
X
X
O1
X
X
Port D5
UART2 data transmit
47
43
31
4
PD6/
UART2_RX
I/O
X
X
X
O1
X
X
Port D6
UART2 data receive
48
44
32
5
PD7/ TLI
[TIM1_CH4]
I/O
X
X
X
O1
X
X
Port D7
Top level interrupt
TIM1_CH4 [AFR4]
Notes:
(1)
A pull-up is applied to PF4 during the reset phase. This pin is input floating after reset release.
(2)
AIN12 is not selectable in ADC scan mode or with analog watchdog.
(3)
In 44-pin package, AIN9 cannot be used by ADC scan mode.
(4)
In the open-drain output column, âTâ defines a true open-drain I/O (P-buffer, weak pull-up and protection diode to V
DD
are not implemented).
(5)
The PD1 pin is in input pull-up during the reset phase and after internal reset release.
DocID14771 Rev 13 23/99