Datasheet

Electrical characteristics STM8S003F3 STM8S003K3
78/103 DocID018576 Rev 5
Figure 38. SPI timing diagram - slave mode and CPHA = 0
Figure 39. SPI timing diagram - slave mode and CPHA = 1
(1)
1. Measurement points are done at CMOS levels: 0.3 V
DD
and 0.7 V
DD.
3. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in Hi-Z.
DLF
^</ŶƉƵƚ
W,сϬ
DK^/
/EWhd
D/^K
KhdW hd
W,сϬ
D^ K hd
D^ /E
/dϲ Khd
>^ /E
>^ Khd
WK>сϬ
WK>сϭ
/ dϭ /E
E^^ŝŶƉƵƚ
ƚ^h;E^^Ϳ
ƚĐ;^<Ϳ
ƚŚ;E^^Ϳ
ƚĂ;^KͿ
ƚǁ;^<,Ϳ
ƚǁ;^<>Ϳ
ƚǀ;^KͿ
ƚŚ;^KͿ
ƚƌ;^<Ϳ
ƚĨ;^<Ϳ
ƚĚŝƐ;^KͿ
ƚƐƵ;^/Ϳ
ƚŚ;^/Ϳ
DL
6&.,QSXW
&3+$ 
026,
,1387
0,62
287 3 87
&3+$ 
06 % 2 87
06% ,1
%, 7 28 7
/6% ,1
/6% 287
&32/ 
&32/ 
%,7 ,1
W
68166
W
F6&.
W
K166
W
D62
W
Z6&.+
W
Z6&./
W
Y62
W
K62
W
U6&.
W
I6&.
W
GLV62
W
VX6,
W
K6,
166LQSXW