Datasheet

Electrical characteristics STM8S003F3 STM8S003K3
78/103 DS7147 Rev 10
Figure 38. SPI timing diagram - slave mode and CPHA = 0
Figure 39. SPI timing diagram - slave mode and CPHA = 1
(1)
1. Measurement points are done at CMOS levels: 0.3 V
DD
and 0.7 V
DD.
3. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in Hi-Z.
ai14135b
NSS input
t
SU(NSS)
tc(SCK)
th(NSS)
SCK input
CPHA=1
CPOL=0
CPHA=1
CPOL=1
t
w(SCKH)
tw(SCKL)
ta(SO)
tv(SO)
th(SO)
tr(SCK)
tf(SCK)
tdis(SO)
MISO
OUTPUT
MOSI
INPUT
t
su(SI)
th(SI)
MSB OUT
MSB IN
BIT6 OUT
LSB OUT
LSB IN
BIT 1 IN
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