Datasheet

Electrical characteristics STM8S003F3 STM8S003K3
82/103 DS7147 Rev 10
9.3.10 10-bit ADC characteristics
Subject to general operating conditions for V
DDA
, f
MASTER
, and T
A
unless otherwise
specified.
Table 45. ADC characteristics
Symbol Parameter Conditions Min Typ Max Unit
f
ADC
ADC clock frequency
V
DDA
= 3 to 5.5 V 1 - 4
MHz
V
DDA
= 4.5 to 5.5 V 1 - 6
V
AIN
Conversion voltage range
(1)
1. During the sample time the input capacitance C
AIN
(3 pF max) can be charged/discharged by the external
source. The internal resistance of the analog source must allow the capacitance to reach its final voltage
level within t
S.
After the end of the sample time t
S
, changes of the analog input voltage have no effect on
the conversion result. Values for the sample clock t
S
depend on programming.
-V
SS
-V
DD
V
C
ADC
Internal sample and hold
capacitor
--3-pF
t
S
(1)
Sampling time
f
ADC
= 4 MHz - 0.75 -
µs
f
ADC
= 6 MHz - 0.5 -
t
STAB
Wakeup time from standby - - 7 - µs
t
CONV
Total conversion time (including
sampling time, 10-bit resolution)
f
ADC
= 4 MHz 3.5 µs
f
ADC
= 6 MHz 2.33 µs
-141/f
ADC
Table 46. ADC accuracy with R
AIN
< 10 kΩ , V
DD
= 5 V
Symbol Parameter Conditions Typ Max
(1)
Unit
|E
T
| Total unadjusted error
(2)
f
ADC
= 2 MHz 1.6 3.5
LSB
f
ADC
= 4 MHz 2.2 4
f
ADC
= 6 MHz 2.4 4.5
|E
O
| Offset error
(2)
f
ADC
= 2 MHz 1.1 2.5
f
ADC
= 4 MHz 1.5 3
f
ADC
= 6 MHz 1.8 3
|E
G
| Gain error
(2)
f
ADC
= 2 MHz 1.5 3
f
ADC
= 4 MHz 2.1 3
f
ADC
= 6 MHz 2.2 4
|E
D
| Differential linearity error
(2)
f
ADC
= 2 MHz 0.7 1.5
f
ADC
= 4 MHz 0.7 1.5
f
ADC
= 6 MHz 0.7 1.5
|E
L
| Integral linearity error
(2)
f
ADC
= 2 MHz 0.6 1.5
f
ADC
= 4 MHz 0.8 2
f
ADC
= 6 MHz 0.8 2