Datasheet

DS7147 Rev 10 11/103
STM8S003F3 STM8S003K3 Block diagram
29
3 Block diagram
Figure 1. STM8S003F3/K3 value line block diagram
XTAL 1-16 MHz
RC int. 16 MHz
RC int. 128 kHz
STM8 core
Debug/SWIM
UART1
I2C
SPI
AWU timer
Reset block
Reset
POR
BOR
Clock controller
Detector
Clock to peripherals and core
400 Kbit/s
8Mbit/s
up to 5
Address and data bus
Window WDG
8 Kbyte
128 byte
1 Kbyte RAM
ADC1
Reset
Single wire
debug interface
program Flash
data EEPROM
16-bit general purpose
16-bit advanced control
timer (TIM1)
timer (TIM2)
8-bit basic timer
(TIM4)
Beeper
1/2/4 kHz beep
Independent WDG
4 CAPCOM
channels
Up to
3 CAPCOM
channels
Up to
+ 3 complementary
outputs
LIN master
channels
SPI emul.