Datasheet

DocID030584 Rev 2 67/84
STM8S001J3 Electrical characteristics
75
Figure 32. SPI timing diagram - slave mode and CPHA = 1
(1)
1. Measurement points are done at CMOS levels: 0.3 V
DD
and 0.7 V
DD.
Figure 33. SPI timing diagram - master mode
(1)
1. Measurement points are done at CMOS levels: 0.3 V
DD
and 0.7 V
DD.
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