Datasheet

Electrical characteristics STM8S001J3
66/84 DocID030584 Rev 2
Figure 31. SPI timing diagram - slave mode and CPHA = 0
t
r(SCK)
t
f(SCK)
SPI clock rise and fall time Capacitive load: C = 30 pF - 25
ns
t
su(NSS)
(1)
NSS setup time Slave mode 4 x t
MASTER
-
t
h(NSS)
(1)
NSS hold time Slave mode 70 -
t
w(SCKH)
(1)
t
w(SCKL)
(1)
SCK high and low time Master mode t
SCK
/2 - 15 t
SCK
/2 + 15
t
su(MI)
(1)
t
su(SI)
(1)
Data input setup time
Master mode 5 -
Slave mode 5 -
t
h(MI)
(1)
t
h(SI)
(1)
Data input hold time
Master mode 7 -
Slave mode 10 -
t
a(SO)
(1)(2)
Data output access time Slave mode - 3 x t
MASTER
t
dis(SO)
(1)(3)
Data output disable time Slave mode 25 -
t
v(SO)
(1)
Data output valid time Slave mode (after enable edge) - 65
t
v(MO)
(1)
Data output valid time Master mode (after enable edge) - 30
t
h(SO)
(1)
Data output hold time
Slave mode (after enable edge) 27 -
t
h(MO)
(1)
Master mode (after enable edge) 11 -
1. Values based on design simulation and/or characterization results, and not tested in production.
2. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data.
3. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in Hi-Z.
Table 39. SPI characteristics (continued)
Symbol Parameter Conditions Min Max Unit
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