Datasheet

Pinouts and pin descriptions STM8S001J3
22/84 DocID030584 Rev 2
Note: The PA2, PB0, PB1, PB2, PB3, PB6, PB7, PC1, PC2, PC7, PD0, PD2, PD4, PD7, PE5 and
PF4 GPIOs should be configured after device reset in output push-pull mode with output
low-state to reduce the device’s consumption and to improve its EMC immunity. The GPIOs
mentioned above are not connected to pins, and they are in input-floating mode after a
device reset.
Note: As several pins provide a connection to multiple GPIOs, the mode selection for any of those
GPIOs impacts all the other GPIOs connected to the same pin. The user is responsible for
the proper setting of the GPIO modes in order to avoid conflicts between GPIOs bonded to
the same pin (including their alternate functions). For example, pull-up enabled on PD1 is
also seen on PC6, PD3 and PD5. Push-pull configuration of PC3 is also seen on PC4 and
PC5, etc.
8
PC6/ SPI_MOSI
[TIM1_ CH1]
I/O X
(4)
X X HS O3 X X Port C6
SPI master
out/slave in
Timer 1 -
channel 1
[AFR0]
PD1/ SWIM
(4)
I/O X X
(4)
X HS O4 X X Port D1
SWIM data
interface
-
PD3/ AIN4/
TIM2_ CH2/
ADC_ ETR
I/O X
(4)
X X HS O3 X X Port D3
Analog input
4/ Timer 2 -
channel
2/ADC
external
trigger
-
PD5/ AIN5/
UART1 _TX
I/O X
(4)
XX HS O3 XX Port D5
Analog input
5/ UART1
data transmit
-
1. I/O pins used simultaneously for high current source/sink must be uniformly spaced around the package. In addition, the total
driven current must respect the absolute maximum ratings.
2. When the MCU is in halt/active-halt mode, PA1 is automatically configured in input weak pull-up and cannot be used for
waking up the device. In this mode, the output state of PA1 is not driven. It is recommended d to use PA1 only in input mode
if halt/active-halt is used in the application.
3. In the open-drain output column, “T” defines a true open-drain I/O (P-buffer, weak pull-up, and protection diode to VDD are
not implemented). Although PB5 itself is a true open drain GPIO with its respective internal circuitry and characteristics, V
IN
maximum of the pin number 5 is limited by the standard GPIO PA3 which is also bonded to pin number 5.
4. The PD1 pin is in input pull-up during the reset phase and after internal reset release. This PD1 default state influences all
GPIOs connected in parallel on pin# 8 (PC6, PD3, PD5).
Table 5. STM8S001J3 pin description (continued)
Pin no.
Pin name Type
Input Output
Main
function
(after
reset)
Default
alternate
function
Alternate
function
after remap
[option bit]
SO8N
floating
wpu
Ext. interr.
High
sink
(1)
Speed
OD PP
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