Datasheet

DS12167 Rev 4 33/94
STM8L050J3 Memory and register map
43
0x00 50C4
CLK
CLK_PCKENR2 CLK Peripheral clock gating register 2 0x00
0x00 50C5 CLK_CCOR CLK Configurable clock control register 0x00
0x00 50C6 CLK_ECKCR CLK External clock control register 0x00
0x00 50C7 CLK_SCSR CLK System clock status register 0x01
0x00 50C8 CLK_SWR CLK System clock switch register 0x01
0x00 50C9 CLK_SWCR CLK Clock switch control register 0xX0
0x00 50CA CLK_CSSR CLK Clock security system register 0x00
0x00 50CB CLK_CBEEPR CLK Clock BEEP register 0x00
0x00 50CC CLK_HSICALR CLK HSI calibration register 0xXX
0x00 50CD CLK_HSITRIMR CLK HSI clock calibration trimming register 0x00
0x00 50CE CLK_HSIUNLCKR CLK HSI unlock register 0x00
0x00 50CF CLK_REGCSR CLK Main regulator control status register
0bxx11 1
00X
0x00 50D0 CLK_PCKENR3 CLK Peripheral clock gating register 3 0x00
0x00 50D1
to
0x00 50D2
Reserved area (2 bytes)
0x00 50D3
WWDG
WWDG_CR WWDG control register 0x7F
0x00 50D4 WWDG_WR WWDR window register 0x7F
0x00 50D5
to
00 50DF
Reserved area (11 bytes)
0x00 50E0
IWDG
IWDG_KR IWDG key register 0x01
0x00 50E1 IWDG_PR IWDG prescaler register 0x00
0x00 50E2 IWDG_RLR IWDG reload register 0xFF
0x00 50E3
to
0x00 50EF
Reserved area (13 bytes)
0x00 50F0
BEEP
BEEP_CSR1 BEEP control/status register 1 0x00
0x00 50F1
0x00 50F2
Reserved area (2 bytes)
0x00 50F3 BEEP_CSR2 BEEP control/status register 2 0x1F
0x00 50F4
to0x00 513F
Reserved area (76 bytes)
0x00 5140
RTC
RTC_TR1 RTC Time register 1 0x00
0x00 5141 RTC_TR2 RTC Time register 2 0x00
0x00 5142 RTC_TR3 RTC Time register 3 0x00
Table 7. General hardware register map (continued)
Address Block Register label Register name
Reset
status
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