Datasheet

Functional overview STM8L050J3
12/94 DS12167 Rev 4
3 Functional overview
Figure 1 presents the basic block diagram which includes all the functional blocks for
STM8L050J3.
Figure 1. STM8L050J3 block diagram
1. Legend:
ADC: Analog-to-digital converter
BOR: Brownout reset
DMA: Direct memory access
I²C: Inter-integrated circuit multimaster interface
IWDG: Independent watchdog
POR/PDR: Power-on reset / power-down reset
RTC: Real-time clock
SPI: Serial peripheral interface
SWIM: Single wire interface module
USART: Universal synchronous asynchronous receiver transmitter
MSv47735V1
Clock
controller
and CSS
Clocks
Address , control and data buses
8-Kbyte
1-Kbyte RAM
to core and
peripherals
IWDG
(38 kHz clock)
Port A
Port B
Port C
Power
VOLT. REG.
WWDG
256-byte
Port D
Beeper
RTC
memoryProgram
Data EEPROM
@V
DD
V
DD18
V
DD
=1.8 V
V
SS
SWIM
SCL, SDA
SPI1_MOSI, SPI1_MISO,
SPI1_SCK
USART1_RX, USART1_TX,
USART1_CK
ADC1_INx
@V
DDA
/V
SSA
12-bit ADC1
3.6 V
PA
PB
PC
PD
BEEP
ALARM
POR/PDR
OSC_IN,
OSC_OUT
OSC32_IN,
OSC32_OUT
to
BOR
PVD
RESET
DMA1 (4 channels)
2 channels
1 channel
Internal reference
voltage
IR_TIM
1-16 MHz oscillator
16 MHz internal RC
32 kHz oscillator
STM8 Core
16-bit Timer 2
38 kHz internal RC
Interrupt controller
16-bit Timer 3
Debug module
(SWIM)
8-bit Timer 4
Infrared interface
SPI1
I²C1
USART1
(2)
(2)
(2)
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