Datasheet

ManualsBrandsST ManualsEmbedded Processors & ControllersMicrocontroller 32bit 512KB LQFP

Pinouts and pin description STM32L496xx

90/272 DS11585 Rev 9

--A9--

- 142 - - VDD12 S - - - -

63 A9 B9 99 D3

143 143 B3 B3 VSS S - - - -

64 A10 A10 100 C4

144 144 A3 A3 VDD S - - - -

-----

- - C2 C2 VSS S - - - -

-----

- - C1 C1 VDD S - - - -

-----

- - A2 A2 PH2 I/O FT - QUADSPI_BK2_IO0, EVENTOUT -

-----

B2 B2 PI7 I/O FT

TIM8_CH3, DCMI_D7, EVENTOUT

-----

B1 B1 PI9 I/O FT

CAN1_RX, EVENTOUT

-----

A1 A1 PI10 I/O FT

EVENTOUT

1. PC13, PC14 and PC15 are supplied through the power switch. Since the switch only sinks a limited amount of current(3 mA), the use of GPIOs PC13 to PC15 in output

mode is limited:

- The speed should not exceed 2 MHz with a maximum load of 30 pF.

- These GPIOs must not be used as current sources (e.g. to drive an LED).

2. After a Backup domain power-up, PC13, PC14 and PC15 operate as GPIOs. Their function then depends on the content of the RTC registers which are not reset by the

system reset. For details on how to manage these GPIOs, refer to the Backup domain and RTC register descriptions in the RM0351 reference manual.

3. OPAMPx_VINM pins are not available as additional functions on pins PA1 and PA7 on UFBGA packages. On UFBGA packages, use the OPAMPx_VINM dedicated pins

available on M3 and M4 balls.

4. After reset, these pins are configured as JTAG/SW debug alternate functions, and the internal pull-up on PA15, PA13, PB4 pins and the internal pull-down on PA14 pin are

activated.

Table 15. STM32L496xx pin definitions (continued)

Pin Number

Pin name

(function after

reset)

Pin type

I/O structure

Notes

Pin functions

LQFP64

WLCSP100

WLCSP100_SMPS

LQFP100

UFBGA132

UFBGA132_SMPS

LQFP144

LQFP144_SMPS

UFBGA169

UFBGA169_SMPS

Alternate functions Additional functions

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