Datasheet

Functional overview STM32L496xx
28/272 DS11585 Rev 9
Stop 1 LPR No Off ON
LSE
LSI
BOR, PVD, PVM
RTC, LCD, IWDG
COMPx (x=1,2)
DAC1
OPAMPx (x=1,2)
USARTx (x=1...5)
(9)
LPUART1
(9)
I2Cx (x=1...4)
(10)
LPTIMx (x=1,2)
***
All other peripherals are
frozen.
Reset pin, all I/Os
BOR, PVD, PVM
RTC, LCD, IWDG
COMPx (x=1..2)
USARTx (x=1...5)
(9)
LPUART1
(9)
I2Cx (x=1...4)
(10)
LPTIMx (x=1,2)
OTG_FS
(11)
SWPMI1
(12)
11.2 µA w/o RTC
11.8 µA w RTC
6.6 µs in SRAM
7.8 µs in Flash
Stop 2 LPR No Off ON
LSE
LSI
BOR, PVD, PVM
RTC, LCD, IWDG
COMPx (x=1..2)
I2C3
(10)
LPUART1
(9)
LPTIM1
***
All other peripherals are
frozen.
Reset pin, all I/Os
BOR, PVD, PVM
RTC, LCD, IWDG
COMPx (x=1..2)
I2C3
(10)
LPUART1
(9)
LPTIM1
2.57 µA w/o RTC
2.86 µA w/RTC
6.8 µs in SRAM
8.2 µs in Flash
Table 4. STM32L496xx modes overview (continued)
Mode Regulator
(1)
CPU Flash SRAM Clocks DMA & Peripherals
(2)
Wakeup source Consumption
(3)
Wakeup time
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