Datasheet
DS11585 Rev 9 21/272
STM32L496xx Functional overview
61
3.6 Multi-AHB bus matrix
The 32-bit multi-AHB bus matrix interconnects all the masters (CPU, DMAs and the
DMA2D) and the slaves (Flash memory, RAM, FMC, QUADSPI, AHB and APB peripherals)
and ensures a seamless and efficient operation even when several high speed peripherals
work simultaneously.
Figure 2. Multi-AHB bus matrix
3.7 Firewall
The device embeds a Firewall which protects code sensitive and secure data from any
access performed by a code executed outside of the protected areas.
Each illegal access generates a reset which kills immediately the detected intrusion.
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