Datasheet
DS11585 Rev 9 205/272
STM32L496xx Electrical characteristics
243
6.3.26 DFSDM characteristics
Unless otherwise specified, the parameters given in Table 91 for DFSDM are derived from
tests performed under the ambient temperature, f
APB2
frequency and V
DD
supply voltage
conditions summarized in
Table 22: General operating conditions.
• Output speed is set to OSPEEDRy[1:0] = 10
• Capacitive load C = 30 pF
• Measurement points are done at CMOS levels: 0.5 VDD
Refer to Section 6.3.14: I/O port characteristics for more details on the input/output alternate
function characteristics (DFSDM1_CKINy, DFSDM1_DATINy, DFSDM1_CKOUT for
DFSDM).
V
44
Segment/Common highest level voltage - V
LCD
-
V
V
34
Segment/Common 3/4 level voltage - 3/4 V
LCD
-
V
23
Segment/Common 2/3 level voltage - 2/3 V
LCD
-
V
12
Segment/Common 1/2 level voltage - 1/2 V
LCD
-
V
13
Segment/Common 1/3 level voltage - 1/3 V
LCD
-
V
14
Segment/Common 1/4 level voltage - 1/4 V
LCD
-
V
0
Segment/Common lowest level voltage - 0 -
1. Guaranteed by design.
2. LCD enabled with 3 V internal step-up active, 1/8 duty, 1/4 bias, division ratio= 64, all pixels active, no LCD connected.
Table 90. LCD controller characteristics
(1)
(continued)
Symbol Parameter Conditions Min Typ Max Unit
Table 91. DFSDM characteristics
(1)
Symbol Parameter Conditions Min Typ Max Unit
f
DFSDMCLK
DFSDM clock - - - f
SYSCLK
MHz
f
CKIN
(1/T
CKIN
)
Input clock
frequency
SPI mode (SITP[1:0] = 01) - -
20
(f
DFSDMCLK
/4)
f
CKOUT
Output clock
frequency
---20MHz
DuCy
CKOUT
Output clock
frequency
duty cycle
-455055%
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