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This is information on a product in full production.

July 2018 DS11585 Rev 9 1/272

STM32L496xx

Ultra-low-power Arm

Cortex

-M4 32-bit MCU+FPU, 100DMIPS,

up to 1MB Flash, 320KB SRAM, USB OTG FS, audio, ext. SMPS

Datasheet - production data

Features

• Ultra-low-power with FlexPowerControl

– 1.71 V to 3.6 V power supply

– -40 °C to 85/125 °C temperature range

– 320 nA in V

BAT

mode: supply for RTC and

32x32-bit backup registers

– 25 nA Shutdown mode (5 wakeup pins)

– 108 nA Standby mode (5 wakeup pins)

– 426 nA Standby mode with RTC

– 2.57 µA Stop 2 mode, 2.86 µA Stop 2 with

RTC

– 91 µA/MHz run mode (LDO Mode)

– 37 A/MHz run mode (@3.3 V SMPS

Mode)

– Batch acquisition mode (BAM)

– 5 µs wakeup from Stop mode

– Brown out reset (BOR) in all modes except

shutdown

– Interconnect matrix

• Core: Arm

32-bit Cortex

-M4 CPU with FPU,

Adaptive real-time accelerator (ART

Accelerator™) allowing 0-wait-state execution

from Flash memory, frequency up to 80 MHz,

MPU, 100 DMIPS and DSP instructions

• Performance benchmark

– 1.25 DMIPS/MHz (Drystone 2.1)

– 273.55 Coremark

(3.42 Coremark/MHz @

80 MHz)

• Energy benchmark

– 279 ULPMark™ CP score

– 80.2 ULPMark™ PP score

• 16 x timers: 2 x 16-bit advanced motor-control,

2 x 32-bit and 5 x 16-bit general purpose,

2 x 16-bit basic, 2 x low-power 16-bit timers

(available in Stop mode), 2 x watchdogs,

SysTick timer

• RTC with HW calendar, alarms and calibration

• Up to 136 fast I/Os, most 5 V-tolerant, up to 14

I/Os with independent supply down to 1.08 V

• Dedicated Chrom-ART Accelerator™ for

enhanced graphic content creation (DMA2D)

• 8- to 14-bit camera interface up to 32 MHz

(black&white) or 10 MHz (color)

• Memories

– Up to 1 MB Flash, 2 banks read-while-

write, proprietary code readout protection

– 320 KB of SRAM including 64 KB with

hardware parity check

– External memory interface for static

memories supporting SRAM, PSRAM,

NOR and NAND memories

– Dual-flash Quad SPI memory interface

• Clock Sources

– 4 to 48 MHz crystal oscillator

– 32 kHz crystal oscillator for RTC (LSE)

– Internal 16 MHz factory-trimmed RC (±1%)

– Internal low-power 32 kHz RC (±5%)

– Internal multispeed 100 kHz to 48 MHz

oscillator, auto-trimmed by LSE (better than

±0.25% accuracy)

– Internal 48 MHz with clock recovery

– 3 PLLs for system clock, USB, audio, ADC

• LCD 8 × 40 or 4 × 44 with step-up converter

• Up to 24 capacitive sensing channels: support

touchkey, linear and rotary touch sensors

• 4 x digital filters for sigma delta modulator

• Rich analog peripherals (independent supply)

– 3 × 12-bit ADC 5 Msps, up to 16-bit with

hardware oversampling, 200 µA/Msps

UFBGA132 (7 × 7)

LQFP144 (20 × 20)

UFBGA169 (7 x 7)

WLCSP100

LQFP100 (14 x 14)

LQFP64 (10 x 10)

www.st.com

Downloaded from Arrow.com.

Summary of content (272 pages)

PAGE 1
STM32L496xx Ultra-low-power Arm® Cortex®-M4 32-bit MCU+FPU, 100DMIPS, up to 1MB Flash, 320KB SRAM, USB OTG FS, audio, ext. SMPS Datasheet - production data Features • Ultra-low-power with FlexPowerControl – 1.71 V to 3.6 V power supply – -40 °C to 85/125 °C temperature range – 320 nA in VBAT mode: supply for RTC and 32x32-bit backup registers – 25 nA Shutdown mode (5 wakeup pins) – 108 nA Standby mode (5 wakeup pins) – 426 nA Standby mode with RTC – 2.57 µA Stop 2 mode, 2.
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STM32L496xx – – – – – – 2 x 12-bit DAC output channels, low-power sample and hold – 2 x operational amplifiers with built-in PGA – 2 x ultra-low-power comparators • 20 x communication interfaces – USB OTG 2.0 full-speed, LPM and BCD – 2 x SAIs (serial audio interface) – 4 x I2C FM+(1 Mbit/s), SMBus/PMBus – 5 x U(S)ARTs (ISO 7816, LIN, IrDA, modem) 1 x LPUART 3 x SPIs (4 x SPIs with the Quad SPI) 2 x CAN (2.
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STM32L496xx Contents Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.1 Arm® Cortex®-M4 core with FPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.
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Contents STM32L496xx 3.17.3 4/272 Downloaded from Arrow.com. VBAT battery voltage monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.18 Digital to analog converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.19 Voltage reference buffer (VREFBUF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3.20 Comparators (COMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 3.21 Operational amplifier (OPAMP) .
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STM32L496xx Contents 3.41.1 Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . 61 3.41.2 Embedded Trace Macrocell™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 4 Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 5 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 6 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . .
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Contents 7 STM32L496xx 6.3.19 Digital-to-Analog converter characteristics . . . . . . . . . . . . . . . . . . . . . 191 6.3.20 Voltage reference buffer characteristics . . . . . . . . . . . . . . . . . . . . . . . . 196 6.3.21 Comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 6.3.22 Operational amplifiers characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 199 6.3.23 Temperature sensor characteristics . . . . . . . . . . . . . . . . . .
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STM32L496xx List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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List of tables Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45. Table 46. Table 47. Table 48. Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. Table 62. Table 63. Table 64. Table 65. Table 66. Table 67. Table 68. Table 69. Table 70. Table 71. Table 72. Table 73. Table 74. Table 75. Table 76. Table 77. Table 78. Table 79. Table 80. Table 81. 8/272 Downloaded from Arrow.com.
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STM32L496xx Table 82. Table 83. Table 84. Table 85. Table 86. Table 87. Table 88. Table 89. Table 90. Table 91. Table 92. Table 93. Table 94. Table 95. Table 96. Table 97. Table 98. Table 99. Table 100. Table 101. Table 102. Table 103. Table 104. Table 105. Table 106. Table 107. Table 108. Table 109. Table 110. Table 111. Table 112. Table 113. Table 114. Table 115. Table 116. Table 117. Table 118. Table 119. Table 120. Table 121. Table 122. Table 123. Table 124. Table 125. Table 126. Table 127. Table 128.
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List of tables STM32L496xx package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260 Table 130. WLCSP100 recommended PCB design rules (0.4 mm pitch) . . . . . . . . . . . . . . . . . . . . . 261 Table 131. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 Table 132. Package thermal characteristics . . . . . . . . . .
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STM32L496xx List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42. Figure 43.
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List of figures Figure 48. Figure 49. Figure 50. Figure 51. Figure 52. Figure 53. Figure 54. Figure 55. Figure 56. Figure 57. Figure 58. Figure 59. Figure 60. Figure 61. Figure 62. Figure 63. Figure 64. Figure 65. Figure 66. Figure 67. Figure 68. Figure 69. Figure 70. Figure 71. Figure 72. Figure 73. Figure 74. Figure 75. Figure 76. Figure 77. Figure 78. Figure 79. Figure 80. Figure 81. Figure 82. 12/272 Downloaded from Arrow.com. STM32L496xx Asynchronous multiplexed PSRAM/NOR read waveforms. . . . . .
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STM32L496xx 1 Introduction Introduction This datasheet provides the ordering information and mechanical device characteristics of the STM32L496xx microcontrollers. This document should be read in conjunction with the STM32L4x6 reference manual (RM0351). The reference manual is available from the STMicroelectronics website www.st.com. For information on the Arm®(a) Cortex®-M4 core, please refer to the Cortex®-M4 Technical Reference Manual, available from the www.arm.com website. a.
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Description 2 STM32L496xx Description The STM32L496xx devices are the ultra-low-power microcontrollers based on the highperformance Arm® Cortex®-M4 32-bit RISC core operating at a frequency of up to 80 MHz. The Cortex-M4 core features a Floating point unit (FPU) single precision which supports all Arm® single-precision data-processing instructions and data types. It also implements a full set of DSP instructions and a memory protection unit (MPU) which enhances application security.
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STM32L496xx Description The STM32L496xx family offers six packages from 64-pin to 169-pin packages. Table 2.
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Description STM32L496xx Table 2. STM32L496xx family device features and peripheral counts (continued) Peripheral STM32L496Ax STM32L496Zx STM32L496Qx Random generator GPIOs(3) Wakeup pins Nb of I/Os down to 1.
PAGE 17
STM32L496xx Description Figure 1. STM32L496xx block diagram )OH[LEOH VWDWLF PHPRU\ FRQWUROOHU )60& 65$0 365$0 125 )ODVK 1$1' )ODVK 1-7567 -7', -7&. 6:&/. -7'2 6:' -7'2 -7$* 6: 038 (70 19,& 75$&(&/. 75$&('> @ &/. 1(> @ 1/ 1%/> @ $> @ '> @ 12( 1:( 1:$,7 1&( ,17 DV $) ' > @ ' > @ &/. &/. &6 YƵĂĚ ^W/ ŵĞŵŽƌǇ ŝŶƚĞƌĨĂĐĞ ' %86 $50 &RUWH[ 0 0+] )38 $57 $&&(/ &$&+( , %86 &/&K +6<1& 96<1& 3,;&/. '> @ &DPHUD ,QWHUIDFH # 9''86% 65$0 .
PAGE 18
Functional overview STM32L496xx 3 Functional overview 3.1 Arm® Cortex®-M4 core with FPU The Arm® Cortex®-M4 with FPU processor is the latest generation of Arm® processors for embedded systems. It was developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced response to interrupts.
PAGE 19
STM32L496xx 3.4 Functional overview Embedded Flash memory STM32L496xx devices feature up to 1 Mbyte of embedded Flash memory available for storing programs and data. The Flash memory is divided into two banks allowing readwhile-write operations. This feature allows to perform a read operation from one bank while an erase or program operation is performed to the other bank. The dual bank boot is also supported. Each bank contains 256 pages of 2 Kbyte.
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Functional overview STM32L496xx The whole non-volatile memory embeds the error correction code (ECC) feature supporting: 3.5 • single error detection and correction • double error detection. • The address of the ECC fail can be read in the ECC register Embedded SRAM STM32L496xx devices feature 320 Kbyte of embedded SRAM. This SRAM is split into two blocks: • 256 Kbyte mapped at address 0x2000 0000 (SRAM1) • 64 Kbyte located at address 0x1000 0000 with hardware parity check (SRAM2).
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STM32L496xx 3.6 Functional overview Multi-AHB bus matrix The 32-bit multi-AHB bus matrix interconnects all the masters (CPU, DMAs and the DMA2D) and the slaves (Flash memory, RAM, FMC, QUADSPI, AHB and APB peripherals) and ensures a seamless and efficient operation even when several high speed peripherals work simultaneously. Figure 2. Multi-AHB bus matrix $50 &257(; 0 ZLWK )38 6 6 6 '0$ '0$ '0$ ' 6 6 6 0 '&RGH $&&(/ 0 ,&RGH )/$6+ 0% 65$0 .% 0 .
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Functional overview STM32L496xx The Firewall main features are the following: • Three segments can be protected and defined thanks to the Firewall registers: – Code segment (located in Flash or SRAM1 if defined as executable protected area) – Non-volatile data segment (located in Flash) – Volatile data segment (located in SRAM1) • The start address and the length of each segments are configurable: – Code segment: up to 1024 Kbyte with granularity of 256 bytes – Non-volatile data segment: up to 1024 Kbyte
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STM32L496xx Functional overview 3.10 Power supply management 3.10.1 Power supply schemes • VDD = 1.71 to 3.6 V: external power supply for I/Os (VDDIO1), the internal regulator and the system analog such as reset, power management and internal clocks. It is provided externally through VDD pins. • VDD12 = 1.05 to 1.32 V: external power supply bypassing internal regulator when connected to an external SMPS.
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Functional overview STM32L496xx Figure 3. Power supply overview 9''$ GRPDLQ 9''$ 966$ $ ' FRQYHUWHUV FRPSDUDWRUV ' $ FRQYHUWHUV RSHUDWLRQDO DPSOLILHUV 9ROWDJH UHIHUHQFH EXIIHU 9/&' /&' 9''86% 966 86% WUDQVFHLYHUV 9'',2 GRPDLQ 9'',2 9'',2 966 , 2 ULQJ 3*> @ 9'' GRPDLQ 9'',2 , 2 ULQJ 9&25( GRPDLQ 5HVHW EORFN 7HPS VHQVRU 3// +6, 06, 966 9'' 9'' 6WDQGE\ FLUFXLWU\ :DNHXS ORJLF ,:'* &RUH 0HPRULHV 'LJLWDO SHULSKHUDOV 9&25( 9ROWDJH UHJXODWRU /RZ YROWDJH GHWHFWRU %DFNXS GRPDLQ 9%$7
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STM32L496xx Functional overview Figure 4. Power-up/down sequence 9 9''; 9'' 9%25 3RZHU RQ ,QYDOLG VXSSO\ DUHD 2SHUDWLQJ PRGH 9''; 9'' P9 3RZHU GRZQ 9''; LQGHSHQGHQW IURP 9'' WLPH 06Y 9 1. VDDX refers to any power supply among VDDA, VDDUSB, VDDIO2, VLCD. 3.10.2 Power supply supervisor The device has an integrated ultra-low-power brown-out reset (BOR) active in all modes except Shutdown and ensuring proper operation after power-on and during power down.
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Functional overview 3.10.3 STM32L496xx Voltage regulator Two embedded linear voltage regulators supply most of the digital circuitries: the main regulator (MR) and the low-power regulator (LPR). • The MR is used in the Run and Sleep modes and in the Stop 0 mode. • The LPR is used in Low-Power Run, Low-Power Sleep, Stop 1 and Stop 2 modes. It is also used to supply the 64 Kbyte SRAM2 in Standby with SRAM2 retention.
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Downloaded from Arrow.com. DS11585 Rev 9 Stop 0 LPSleep Sleep LPRun Run Mode MR Range 2(8) MR Range 1(8) LPR SMPS range 2 Low MR range2 SMPS range 2 High MR range 1 LPR SMPS range 2 Low MR range2 SMPS range 2 High MR range 1 Regulator(1) No No No Yes Yes CPU OFF ON(4) ON(4) ON(4) ON(4) ON ON(7) ON(7) ON ON LSE LSI Any except PLL Any Any except PLL Any Flash SRAM Clocks Any interrupt or event Reset pin, all I/Os BOR, PVD, PVM RTC, LCD, IWDG COMPx (x=1..
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/272 Downloaded from Arrow.com. LPR LPR Stop 1 Stop 2 Regulator Mode (1) No No CPU Off Off ON ON LSE LSI LSE LSI Flash SRAM Clocks Wakeup source Reset pin, all I/Os BOR, PVD, PVM RTC, LCD, IWDG COMPx (x=1..2) USARTx (x=1...5)(9) LPUART1(9) I2Cx (x=1...4)(10) LPTIMx (x=1,2) OTG_FS(11) SWPMI1(12) Reset pin, all I/Os BOR, PVD, PVM RTC, LCD, IWDG COMPx (x=1..2) I2C3(10) LPUART1(9) LPTIM1 DMA & Peripherals(2) BOR, PVD, PVM RTC, LCD, IWDG COMPx (x=1,2) DAC1 OPAMPx (x=1,2) USARTx (x=1...
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Downloaded from Arrow.com. OFF OFF LPR Regulator Power ed Off Power ed Off CPU Reset pin 5 I/Os (WKUPx)(14) RTC RTC *** All other peripherals are powered off. *** I/O configuration can be floating, pull-up or pulldown(14) Off Power ed Off Power ed Off Reset pin 5 I/Os (WKUPx)(13) BOR, RTC, IWDG LSE LSE LSI BOR, RTC, IWDG *** All other peripherals are powered off.
PAGE 30
Functional overview STM32L496xx By default, the microcontroller is in Run mode after a system or a power Reset. It is up to the user to select one of the low-power modes described below: • Sleep mode In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can wake up the CPU when an interrupt/event occurs. • Low-power run mode This mode is achieved with VCORE supplied by the low-power regulator to minimize the regulator's operating current.
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STM32L496xx • Functional overview Shutdown mode The Shutdown mode allows to achieve the lowest power consumption. The internal regulator is switched off so that the VCORE domain is powered off. The PLL, the HSI16, the MSI, the LSI and the HSE oscillators are also switched off. The RTC can remain active (Shutdown mode with RTC, Shutdown mode without RTC). The BOR is not available in Shutdown mode. No power voltage monitoring is possible in this mode, therefore the switch to Backup domain is not supported.
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Functional overview STM32L496xx Table 5.
PAGE 33
STM32L496xx Functional overview Table 5.
PAGE 34
Functional overview STM32L496xx Table 5.
PAGE 35
STM32L496xx Functional overview An internal VBAT battery charging circuit is embedded and can be activated when VDD is present. Note: When the microcontroller is supplied from VBAT, external interrupts and RTC alarm/events do not exit it from VBAT operation. 3.11 Interconnect matrix Several peripherals have direct connections between them. This allows autonomous communication between peripherals, saving CPU resources thus power supply consumption.
PAGE 36
Functional overview STM32L496xx Sleep Low-power run Low-power sleep Stop 0 / Stop 1 Stop 2 Interconnect source Run Table 6.
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STM32L496xx 3.12 Functional overview Clocks and startup The clock controller (see Figure 5) distributes the clocks coming from different oscillators to the core and the peripherals. It also manages clock gating for low-power modes and ensures clock robustness.
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Functional overview STM32L496xx interrupt is generated if enabled. LSE failure can also be detected and generated an interrupt. • Clock-out capability: – MCO: microcontroller clock output: it outputs one of the internal clocks for external use by the application. Low frequency clocks (LSI, LSE) are available down to Stop 1 low power state. – LSCO: low speed clock output: it outputs LSI or LSE in all low-power modes down to Standby mode. LSE can also be output on LSCO in Shutdown mode.
PAGE 39
STM32L496xx Functional overview Figure 5. Clock tree WR ,:'* >^/ Z ϯϮ Ŭ,ǌ /6&2 WR 57& DQG /&' 26& B287 >^ K^ ϯϮ͘ϳϲϴ Ŭ,ǌ ͬϯϮ 26& B,1 0&2 WR 3:5 /6( /6, 06, +6, +6( 6<6&/. ĺ WR $+% EXV FRUH PHPRU\ DQG '0$ , WZ ^ ͬ ϭ͕Ϯ͕͘͘ϱϭϮ +&/. 3//&/. +6, ,^ K^ ϰͲϰϴ D,ǌ 26&B,1 ůŽĐŬ ĚĞƚĞĐƚŽƌ WR &RUWH[ V\VWHP WLPHU ͬ ϴ ůŽĐŬ ƐŽƵƌĐĞ ĐŽŶƚƌŽů 26&B287 )&/. &RUWH[ IUHH UXQQLQJ FORFN W ϭ WZ ^ ͬ ϭ͕Ϯ͕ϰ͕ϴ͕ϭϲ 3&/. WR $3% SHULSKHUDOV ǆϭ Žƌ ǆϮ +6( 06, +6, 6<6&/. /6( +6, 6<6&/.
PAGE 40
Functional overview 3.13 STM32L496xx General-purpose inputs/outputs (GPIOs) Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog alternate functions. Fast I/O toggling can be achieved thanks to their mapping on the AHB2 bus.
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STM32L496xx 3.15 Functional overview Chrom-ART Accelerator™ (DMA2D) The Chrom-Art Accelerator™ (DMA2D) is a graphic accelerator which offers advanced bit blitting, row data copy and pixel format conversion. It supports the following functions: • Rectangle filling with a fixed color • Rectangle copy • Rectangle copy with pixel format conversion • Rectangle composition with blending and pixel format conversion.
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Functional overview 3.17 STM32L496xx Analog to digital converter (ADC) The device embeds 3 successive approximation analog-to-digital converters with the following features: • 12-bit native resolution, with built-in calibration • 5.33 Msps maximum conversion rate with full resolution Down to 18.75 ns sampling time – Increased conversion rate for lower resolution (up to 8.88 Msps for 6-bit resolution) • Up to 24 external channels, some of them shared between ADC1 and ADC2, or ADC1, ADC2 and ADC3.
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STM32L496xx Functional overview To improve the accuracy of the temperature sensor measurement, each device is individually factory-calibrated by ST. The temperature sensor factory calibration data are stored by ST in the system memory area, accessible in read-only mode. Table 8. Temperature sensor calibration values 3.17.2 Calibration value name Description Memory address TS_CAL1 TS ADC raw data acquired at a temperature of 30 °C (± 5 °C), VDDA = VREF+ = 3.
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Functional overview STM32L496xx This digital interface supports the following features: • Up to two DAC output channels • 8-bit or 12-bit output mode • Buffer offset calibration (factory and user trimming) • Left or right data alignment in 12-bit mode • Synchronized update capability • Noise-wave generation • Triangular-wave generation • Dual DAC channel independent or simultaneous conversions • DMA capability for each channel • External triggers for conversion • Sample and hold low-p
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STM32L496xx 3.20 Functional overview Comparators (COMP) The STM32L496xx devices embed two rail-to-rail comparators with programmable reference voltage (internal or external), hysteresis and speed (low speed for low-power) and with selectable output polarity. The reference voltage can be one of the following: • External I/O • DAC output channels • Internal reference voltage or submultiple (1/4, 1/2, 3/4).
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Functional overview STM32L496xx The main features of the touch sensing controller are the following: • Proven and robust surface charge transfer acquisition principle • Supports up to 24 capacitive sensing channels • Up to 3 capacitive sensing channels can be acquired in parallel offering a very good response time • Spread spectrum feature to improve system robustness in noisy environments • Full hardware management of the charge transfer acquisition sequence • Programmable charge transfer freq
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STM32L496xx Functional overview hardware. DFSDM features optional parallel data stream inputs from microcontrollers memory (through DMA/CPU transfers into DFSDM or from internal ADCs). DFSDM transceivers support several serial interface formats (to support various Σ∆ modulators). DFSDM digital filter modules perform digital processing according user selected filter parameters with up to 24-bit final ADC resolution.
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Functional overview STM32L496xx without having any impact on the timing of “injected” conversions – 3.25 “injected” conversions for precise timing and with high conversion priority Random number generator (RNG) All devices embed an RNG that delivers 32-bit random numbers generated by an integrated analog circuit. 3.
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STM32L496xx Functional overview Table 10. Timer feature comparison (continued) Timer type Timer Counter resolution Counter type Prescaler factor DMA request generation Capture/ compare channels Complementary outputs Generalpurpose TIM16, TIM17 16-bit Up Any integer between 1 and 65536 Yes 1 1 Basic TIM6, TIM7 16-bit Up Any integer between 1 and 65536 Yes 0 No 3.27.
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Functional overview 3.27.2 STM32L496xx General-purpose timers (TIM2, TIM3, TIM4, TIM5, TIM15, TIM16, TIM17) There are up to seven synchronizable general-purpose timers embedded in the STM32L496xx (see Table 10 for differences). Each general-purpose timer can be used to generate PWM outputs, or act as a simple time base.
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STM32L496xx Functional overview This low-power timer supports the following features: 3.27.5 • 16-bit up counter with 16-bit autoreload register • 16-bit compare register • Configurable output: pulse, PWM • Continuous/ one shot mode • Selectable software/hardware input trigger • Selectable clock source – Internal clock sources: LSE, LSI, HSI16 or APB clock – External clock source over LPTIM input (working even with no internal clock source running, used by pulse counter application).
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Functional overview 3.28 STM32L496xx Real-time clock (RTC) and backup registers The RTC is an independent BCD timer/counter. It supports the following features: • Calendar with subsecond, seconds, minutes, hours (12 or 24 format), week day, date, month, year, in BCD (binary-coded decimal) format. • Automatic correction for 28, 29 (leap year), 30, and 31 days of the month. • Two programmable alarms. • On-the-fly correction from 1 to 32767 RTC clock pulses.
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STM32L496xx 3.29 Functional overview Inter-integrated circuit interface (I2C) The device embeds four I2C. Refer to Table 11: I2C implementation for the features implementation. The I2C bus interface handles communications between the microcontroller and the serial I2C bus. It controls all I2C bus-specific sequencing, protocol, arbitration and timing. The I2C peripheral supports: • • I2C-bus specification and user manual rev.
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Functional overview 3.30 STM32L496xx Universal synchronous/asynchronous receiver transmitter (USART) The STM32L496xx devices have three embedded universal synchronous receiver transmitters (USART1, USART2 and USART3) and two universal asynchronous receiver transmitters (UART4, UART5). These interfaces provide asynchronous communication, IrDA SIR ENDEC support, multiprocessor communication mode, single-wire half-duplex communication mode and have LIN Master/Slave capability.
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STM32L496xx 3.31 Functional overview Low-power universal asynchronous receiver transmitter (LPUART) The device embeds one Low-Power UART. The LPUART supports asynchronous serial communication with minimum power consumption. It supports half duplex single wire communication and modem operations (CTS/RTS). It allows multiprocessor communication. The LPUART has a clock domain independent from the CPU clock, and can wakeup the system from Stop mode using baudrates up to 220 Kbaud.
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Functional overview 3.32 STM32L496xx Serial peripheral interface (SPI) Three SPI interfaces allow communication up to 40 Mbits/s in master and up to 24 Mbits/s slave modes, in half-duplex, full-duplex and simplex modes. The 3-bit prescaler gives 8 master mode frequencies and the frame size is configurable from 4 bits to 16 bits. The SPI interfaces support NSS pulse mode, TI mode and Hardware CRC calculation. All SPI interfaces can be served by the DMA controller. 3.
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STM32L496xx Functional overview Table 13. SAI implementation SAI features(1) SAI1 SAI2 I2S, LSB or MSB-justified, PCM/DSP, TDM, AC’97 X X Mute mode X X Stereo/Mono audio frame capability. X X 16 slots X X Data size configurable: 8-, 10-, 16-, 20-, 24-, 32-bit X X X (8 Word) X (8 Word) X X FIFO Size SPDIF 1. X: supported 3.
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Functional overview STM32L496xx Dual CAN peripheral configuration is available. The CAN peripheral supports: • Supports CAN protocol version 2.0 A, B Active • Bit rates up to 1 Mbit/s • Transmission • • • 3.
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STM32L496xx Functional overview The synchronization for this oscillator can also be taken from the USB data stream itself (SOF signalization) which allows crystal less operation. The major features are: • Combined Rx and Tx FIFO size of 1.
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Functional overview STM32L496xx LCD parallel interface The FMC can be configured to interface seamlessly with most graphic LCD controllers. It supports the Intel 8080 and Motorola 6800 modes, and is flexible enough to adapt to specific LCD interfaces. This LCD parallel interface capability makes it easy to build cost effective graphic applications using LCD modules with embedded controllers or high performance solutions using external controllers with dedicated acceleration. 3.
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STM32L496xx Functional overview 3.41 Development support 3.41.1 Serial wire JTAG debug port (SWJ-DP) The Arm® SWJ-DP interface is embedded, and is a combined JTAG and serial wire debug port that enables either a serial wire debug or a JTAG probe to be connected to the target.
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Pinouts and pin description 4 STM32L496xx Pinouts and pin description Figure 7.
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STM32L496xx Pinouts and pin description 9'' 966 3( 3( 3% 3% 3+ %227 3% 3% 3% 3% 3% 3* 9'',2 966 3* 3* 3* 3* 3* 3* 3' 3' 9'' 966 3' 3' 3' 3' 3' 3' 3& 3& 3& 3$ 3$ Figure 9.
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Pinouts and pin description STM32L496xx 9'' 966 9'' 3( 3( 3% 3% 3+ %227 3% 3% 3% 3% 3% 9'',2 966 3* 3* 3* 3* 3* 3* 3' 3' 9'' 966 3' 3' 3' 3' 3' 3' 3& 3& 3& 3$ 3$ Figure 10.
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STM32L496xx Pinouts and pin description Figure 11.
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Pinouts and pin description STM32L496xx 9'' 966 3( 3( 3% 3% 3+ %227 3% 3% 3% 3% 3% 3' 3' 3' 3' 3' 3' 3' 3' 3& 3& 3& 3$ 3$ Figure 13.
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STM32L496xx Pinouts and pin description Figure 14.
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Pinouts and pin description STM32L496xx 9'' 966 3% 3% 3+ %227 3% 3% 3% 3% 3% 3' 3& 3& 3& 3$ 3$ Figure 16.
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STM32L496xx Pinouts and pin description Table 14. Legend/abbreviations used in the pinout table Name Pin name Abbreviation Definition Unless otherwise specified in brackets below the pin name, the pin function during and after reset is the same as the actual pin name S Supply pin I Input only pin Pin type I/O Input / output pin FT 5 V tolerant I/O TT 3.
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C8 D8 E7 C10 C9 D10 - - 1 2 3 - - B9 - B10 - LQFP64 - WLCSP100 WLCSP100_SMPS DS11585 Rev 9 D10 C9 C10 D8 E8 E7 B10 C8 - LQFP100 8 7 6 5 4 3 2 1 - D1 C1 E2 D2 C2 B1 A1 B2 - 2 3 4 5 6 7 8 B1 C2 D2 E2 C1 D1 1 B2 A1 - - Pin Number UFBGA132 Downloaded from Arrow.com.
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- - - D9 E9 - - - - - - - - - - - - - - - - E10 LQFP64 - WLCSP100 4 WLCSP100_SMPS DS11585 Rev 9 - - - E9 E10 - - - - - - D9 LQFP100 - - - 11 10 - - - - - - 9 - - - G2 F2 F4 F3 E4 D4 D5 D6 E1 UFBGA132 13 14 15 16 17 18 19 20 E4 F3 F4 F2 G2 - 11 D5 12 10 D6 D4 9 E1 Pin Number UFBGA132_SMPS Downloaded from Arrow.com.
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F9 F8 H10 F7 8 9 10 11 5 E8 F10 - 7 - - G10 - LQFP64 6 WLCSP100 WLCSP100_SMPS DS11585 Rev 9 F6 G9 F7 G10 F8 F9 F10 - - LQFP100 18 17 16 15 14 13 12 - - K2 J3 J2 H1 H2 G1 F1 - - 25 26 27 28 29 H2 H1 J2 J3 K2 23 F1 24 22 - G1 21 - Pin Number UFBGA132 Downloaded from Arrow.com.
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- G9 - H8 H7 14 - 15 16 G7 - 13 G8 - J10 H9 LQFP64 - WLCSP100 12 WLCSP100_SMPS DS11585 Rev 9 H8 G7 - G8 - J10 H10 - H9 LQFP100 25 24 - 23 - 22 21 20 19 K3 M2 M3 L2 - M1 L1 - J1 UFBGA132 - 34 - 35 36 - L2 M3 M2 K3 32 L1 33 31 - M1 30 J1 Pin Number UFBGA132_SMPS Downloaded from Arrow.com.
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F6 G6 K9 - 21 22 - 18 20 K10 17 J8 J9 LQFP64 19 WLCSP100 WLCSP100_SMPS DS11585 Rev 9 - K9 J7 H7 J8 K10 J9 LQFP100 - 31 30 29 28 27 26 M4 L4 K4 J4 H3 E3 L3 39 40 41 42 - J4 K4 L4 M4 38 E3 H3 37 L3 Pin Number UFBGA132 Downloaded from Arrow.com.
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J6 K7 F5 - - 26 27 28 - - H6 24 K8 J7 LQFP64 25 WLCSP100 23 WLCSP100_SMPS DS11585 Rev 9 - - J6 K7 H6 - K8 G6 LQFP100 - - 37 36 35 34 33 32 J7 K6 L6 M6 M5 L5 K5 J5 UFBGA132 45 46 47 48 49 50 M5 M6 L6 K6 J7 44 K5 L5 43 J5 Pin Number UFBGA132_SMPS Downloaded from Arrow.com.
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- - K6 K5 J5 - - - - - - - - - - - - - - - - - - LQFP64 - WLCSP100 WLCSP100_SMPS DS11585 Rev 9 - - J5 K5 K6 - - - - - - - LQFP100 - - 40 39 38 - - - - - - - G6 F6 M8 L7 M7 G9 H9 J9 J8 K7 - - 55 56 57 58 59 60 61 62 J9 H9 G9 M7 L7 M8 F6 G6 53 K7 54 52 - J8 51 - Pin Number UFBGA132 Downloaded from Arrow.com.
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G4 J4 H4 K3 - - - 29 K4 - G5 H5 LQFP64 - WLCSP100 - WLCSP100_SMPS DS11585 Rev 9 K3 H4 G4 G5 J4 K4 H5 LQFP100 47 46 45 44 43 42 41 L10 M12 M11 M10 L9 M9 L8 UFBGA132 65 66 67 68 69 M10 M11 M12 L10 64 M9 L9 63 L8 Pin Number UFBGA132_SMPS Downloaded from Arrow.com.
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WLCSP100 J3 - - - - - - - - - K2 K1 LQFP64 30 - - - - - - - - - 31 32 WLCSP100_SMPS DS11585 Rev 9 J2 K2 - - - - - - - - K1 J3 LQFP100 50 49 - - - - - - - - - 48 G12 F12 - - - - - - - - - L11 70 71 72 - L11 F12 G12 Pin Number UFBGA132 Downloaded from Arrow.com.
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DS11585 Rev 9 H2 H1 35 36 J1 33 J2 - LQFP64 34 WLCSP100 - WLCSP100_SMPS H3 H1 H2 J1 - LQFP100 54 53 52 51 - K10 K11 K12 L12 - UFBGA132 74 75 76 K11 K10 73 L12 K12 - - Pin Number UFBGA132_SMPS Downloaded from Arrow.com.
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- - - - F1 G3 - - - - - - - G2 - G1 H3 LQFP64 - WLCSP100 WLCSP100_SMPS DS11585 Rev 9 F3 F1 - - - - G1 G2 G3 LQFP100 61 - - 60 59 58 57 56 55 H11 - - H12 J10 J11 J12 K8 K9 79 80 81 82 83 84 85 J11 J10 H12 H11 78 K8 J12 77 K9 Pin Number UFBGA132 Downloaded from Arrow.com.
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- - - - - - F2 - - - - - 37 - - - - - - F4 LQFP64 - WLCSP100 - WLCSP100_SMPS DS11585 Rev 9 F4 - - - - - - - - - F2 LQFP100 63 - - - - - - - - - 62 E12 - - J6 H4 G4 E9 F10 F9 G10 H10 UFBGA132 90 91 92 93 94 95 96 E9 G4 H4 J6 - E12 88 F9 89 87 G10 F10 86 H10 Pin Number UFBGA132_SMPS Downloaded from Arrow.com.
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WLCSP100 F3 E1 E2 E3 D3 D2 LQFP64 38 39 40 41 42 43 WLCSP100_SMPS DS11585 Rev 9 D2 D3 E3 E2 E1 E4 LQFP100 69 68 67 66 65 64 C12 D10 D11 D12 E10 E11 97 98 99 100 101 102 E11 E10 D12 D11 D10 C12 Pin Number UFBGA132 Downloaded from Arrow.com.
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B1 A1 - - - - - - 47 48 - - - - - - C1 45 C2 D1 LQFP64 46 WLCSP100 44 WLCSP100_SMPS DS11585 Rev 9 - - - - - - A1 B1 C2 C1 D1 LQFP100 - - - - 75 74 73 - 72 71 70 - - - - G11 F11 C11 - A11 A12 B12 UFBGA132 105 106 107 108 - C11 F11 G11 - 104 A12 A11 103 B12 Pin Number UFBGA132_SMPS Downloaded from Arrow.com.
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- - - - - - B2 - - - - - - 49 - - - - - - - - - LQFP64 - WLCSP100 WLCSP100_SMPS DS11585 Rev 9 B2 - - - - - - - - - - - LQFP100 76 - - - - - - - - - - - A10 - - - - - - - - - - - - 109 - A10 - - - - - - - Pin Number UFBGA132 Downloaded from Arrow.com.
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D4 C3 C4 B3 A3 52 53 - - A2 LQFP64 51 WLCSP100 50 WLCSP100_SMPS DS11585 Rev 9 A3 B3 C4 D4 C3 A2 LQFP100 82 81 80 79 78 77 B9 C9 B10 C10 B11 A9 UFBGA132 111 112 113 114 115 B11 C10 B10 C9 B9 110 A9 Pin Number UFBGA132_SMPS Downloaded from Arrow.com.
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WLCSP100 E4 - B4 E5 - A4 D5 C5 LQFP64 54 - - - - - - - WLCSP100_SMPS DS11585 Rev 9 C6 B5 A4 - B4 C5 - D5 LQFP100 88 87 - - 86 85 84 83 A5 B6 - - A6 B7 B8 C8 116 117 118 119 120 121 122 123 C8 B8 B7 A6 - B6 A5 Pin Number UFBGA132 Downloaded from Arrow.com.
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B6 - - - A6 - - - - - - - A5 - D6 B5 LQFP64 - WLCSP100 - WLCSP100_SMPS DS11585 Rev 9 - A6 - - - B6 E5 A5 D6 LQFP100 - - - - - - - - - K1 G7 F7 C6 C7 D7 G3 D8 D9 UFBGA132 126 127 128 129 130 131 132 D7 C7 F7 G7 K1 125 D8 G3 124 D9 Pin Number UFBGA132_SMPS Downloaded from Arrow.com.
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B7 A7 57 58 55 C7 C6 LQFP64 56 WLCSP100 WLCSP100_SMPS DS11585 Rev 9 A7 C7 E6 F5 LQFP100 92 91 90 89 B5 C5 A7 A8 134 135 136 A7 C5 B5 133 A8 Pin Number UFBGA132 Downloaded from Arrow.com.
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E6 B8 A8 - - - 61 62 - - - D7 LQFP64 60 WLCSP100 59 WLCSP100_SMPS DS11585 Rev 9 - - - A8 B8 D7 B7 LQFP100 98 97 - 96 95 94 93 A2 C3 - B3 A3 A4 B4 UFBGA132 138 139 140 - 141 142 A4 A3 B3 C6 C3 A2 137 B4 Pin Number UFBGA132_SMPS Downloaded from Arrow.com.
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DS11585 Rev 9 - - - - - - WLCSP100_SMPS - - - - - - A10 B9 A9 LQFP100 - - - - - - 100 99 - - - - - - - C4 D3 - - - 144 C4 - 143 D3 - - - LQFP144_SMPS - - - - - - 144 143 142 UFBGA169 B2 B1 A1 B1 A1 A2 C1 C2 A3 B3 - UFBGA169_SMPS B2 A2 C1 C2 A3 B3 - PI10 PI9 PI7 PH2 VDD VSS VDD VSS VDD12 (function after reset) Pin name Pin type I/O I/O I/O I/O S S S S S I/O structure FT FT FT FT - - - - - - - - - - - - -
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Downloaded from Arrow.com. DS11585 Rev 9 - - - - - - - - - - - PI1 PI2 PI3 PI4 PI5 PI6 PI7 PI8 PI9 PI10 PI11 AF1 - - - - - - - - - - - - TIM1/2/5/8/ LPTIM1 1. Please refer to Table 17 for AF8 to AF15.
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/272 Downloaded from Arrow.com. DS11585 Rev 9 - - - - - - - - - - - PI1 PI2 PI3 PI4 PI5 PI6 PI7 PI8 PI9 PI10 PI11 - - - - - - - - - - - CAN1_RX 1. Please refer to Table 16 for AF0 to AF7.
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STM32L496xx 5 Memory mapping Memory mapping Figure 17.
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Memory mapping STM32L496xx Table 18. STM32L496xx memory map and peripheral register boundary addresses(1) Bus AHB4 AHB3 - AHB2 - AHB1 110/272 Downloaded from Arrow.com.
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STM32L496xx Memory mapping Table 18.
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Memory mapping STM32L496xx Table 18. STM32L496xx memory map and peripheral register boundary addresses(1) (continued) Bus APB1 112/272 Downloaded from Arrow.com.
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STM32L496xx Memory mapping Table 18.
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Electrical characteristics STM32L496xx 6 Electrical characteristics 6.1 Parameter conditions Unless otherwise specified, all voltages are referenced to VSS. 6.1.1 Minimum and maximum values Unless otherwise specified, the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at TA = 25 °C and TA = TAmax (given by the selected temperature range).
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STM32L496xx 6.1.6 Electrical characteristics Power supply scheme Figure 20. Power supply scheme 9%$7 9%$7 9%$7 ĂĐŬƵƉ ĐŝƌĐƵŝƚƌǇ ĂĐŬƵƉ ĐŝƌĐƵŝƚƌǇ ;>^ ͕ Zd ͕ %DFNXS FLUFXLWU\ ;>^ ͕ Zd ͕ ĂĐŬƵƉ ƌĞŐŝƐƚĞƌƐͿ /6( 57& ĂĐŬƵƉ ƌĞŐŝƐƚĞƌƐͿ %DFNXS UHJLVWHUV ϭ͘ϱϱ ʹ ϯ͘ϲ s ϭ͘ϱϱ ʹ ϯ͘ϲ s ± 9 99'' '' WŽǁĞƌ ƐǁŝƚĐŚ WŽǁĞƌ ƐǁŝƚĐŚ 3RZHU VZLWFK [ 9'' 99&25( &25( Q [ 9'' Q [ 9'' ϭ͘Ϭϱ ʹ ϭ͘ϯϮ s ZĞŐƵůĂƚŽƌ 5HJXODWRU ZĞŐƵůĂƚŽƌ ,1 /E [ ) [ ) /HYHO VKLIWHU /HYHO VKLIWHU Q [ 9'' *3,2V *3,2V ,2
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Electrical characteristics 6.1.7 STM32L496xx Current consumption measurement Figure 21. Current consumption measurement scheme with and without external SMPS power supply ,''B86% ,''B86% 9''86% 9''86% ,''B9%$7 ,''B9%$7 9%$7 9%$7 ,'' ,'' ,''$ 6036 9'' 9'' 9'' 9'',2 9'',2 ,''$ 9''$ 9''$ 06Y 9 The IDD_ALL parameters given in Table 26 to Table 48 represent the total MCU consumption including the current supplying VDD, VDDIO2, VDDA, VDDUSB and VBAT. 6.
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STM32L496xx Electrical characteristics Table 19. Voltage characteristics(1) Symbol Ratings VDDX - VSS External main supply voltage (including VDD, VDDA, VDDIO2, VDDUSB, VLCD, VBAT) VDD12 - VSS External SMPS supply voltage VIN(2) Min Max -0.3 4.0 Range 1 -0.3 Range 2 -0.3 Unit 1.4 Input voltage on FT_xxx pins VSS-0.3 min (VDD, VDDA, VDDIO2, VDDUSB, VLCD) + 4.0(3)(4) Input voltage on TT_xx pins VSS-0.3 4.0 Input voltage on BOOT0 pin VSS 9.0 VSS-0.3 4.
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Electrical characteristics STM32L496xx 3. This current consumption must be correctly distributed over all I/Os and control pins. The total output current must not be sunk/sourced between two consecutive power supply pins referring to high pin count QFP packages. 4. Positive injection (when VIN > VDDIOx) is not possible on these I/Os and does not occur for input voltages lower than the specified maximum value. 5. A negative injection is induced by VIN < VSS. IINJ(PIN) must never be exceeded.
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STM32L496xx Electrical characteristics Table 22. General operating conditions (continued) Symbol VBAT Parameter Conditions Min Max - 1.55 3.6 3.0 3.6 0 3.6 -0.3 VDDIOx+0.3 0 9 -0.3 Min(Min(VDD, VDDA, VDDIO2, VDDUSB, VLCD)+3.6 V, 5.
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Electrical characteristics 6.3.2 STM32L496xx Operating conditions at power-up / power-down The parameters given in Table 23 are derived from tests performed under the ambient temperature condition summarized in Table 22. Table 23.
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STM32L496xx Electrical characteristics Table 24. Embedded reset and power control block characteristics (continued) Conditions(1) Min Typ Max Rising edge 2.26 2.31 2.36 Falling edge 2.15 2.20 2.25 Rising edge 2.41 2.46 2.51 Falling edge 2.31 2.36 2.41 Rising edge 2.56 2.61 2.66 Falling edge 2.47 2.52 2.57 Rising edge 2.69 2.74 2.79 Falling edge 2.59 2.64 2.69 Rising edge 2.85 2.91 2.96 Falling edge 2.75 2.81 2.86 Rising edge 2.92 2.98 3.04 Falling edge 2.
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Electrical characteristics 6.3.4 STM32L496xx Embedded voltage reference The parameters given in Table 25 are derived from tests performed under the ambient temperature and supply voltage conditions summarized in Table 22: General operating conditions. Table 25. Embedded internal voltage reference Symbol VREFINT Parameter Internal reference voltage Conditions –40 °C < TA < +130 °C Min Typ Max Unit 1.182 1.212 1.
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STM32L496xx Electrical characteristics Figure 22. VREFINT versus temperature 9 0HDQ DS11585 Rev 9 0LQ 0D[ & 06Y 9 123/272 243 Downloaded from Arrow.com.
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Electrical characteristics 6.3.5 STM32L496xx Supply current characteristics The current consumption is a function of several parameters and factors such as the operating voltage, ambient temperature, I/O pin loading, device software configuration, operating frequencies, I/O pin switching rate, program location in memory and executed binary code. The current consumption is measured as described in Figure 21: Current consumption measurement scheme with and without external SMPS power supply.
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Downloaded from Arrow.com. DS11585 Rev 9 - 0.33 0.23 0.14 9.44 8.52 7.61 5.72 3.87 2.94 2.01 274 158 88.2 63 1 MHz 100 kHz 80 MHz 72 MHz 64 MHz Range 1 48 MHz 32 MHz 24 MHz 16 MHz 2 MHz 1 MHz 400 kHz 100 kHz 0.91 8 MHz 2 MHz 1.68 16 MHz 0.52 2.65 26 MHz 90.6 123 195 307 2.06 2.99 3.92 5.78 7.67 8.59 9.5 0.17 0.26 0.36 0.55 0.94 1.72 2.
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/272 Downloaded from Arrow.com. DS11585 Rev 9 Supply current in Run mode IDD_ALL(Run) fHCLK = fHSE up to 48MHz included, bypass mode PLL ON above 48 MHz all peripherals disable - Conditions(1) 2.06 1.39 48 MHz 32 MHz 0.39 0.22 0.14 0.10 0.06 8 MHz 4 MHz 2 MHz 1 MHz 100 kHz 0.72 2.74 64 MHz 16 MHz 3.06 72 MHz 1.06 3.39 80 MHz 24 MHz 25 °C fHCLK 0.07 0.11 0.16 0.24 0.41 0.74 1.07 1.41 2.08 2.76 3.09 3.42 55 °C 0.13 0.16 0.21 0.29 0.46 0.79 1.13 1.46 2.14 2.
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Downloaded from Arrow.com. DS11585 Rev 9 - 0.3 9.02 7.59 0.27 0.14 10 9.02 8.94 7.51 5.38 4.07 2.86 378 213 101 62 1 MHz 100 kHz 80 MHz 72 MHz 64 MHz Range 1 48 MHz 32 MHz 24 MHz 16 MHz 2 MHz 1 MHz 400 kHz 100 kHz 95.8 144 246 412 2.92 4.12 5.45 9.1 10.1 0.18 0.44 0.41 0.73 1.26 2 MHz 1.22 8 MHz 2.23 3.14 0.69 3.1 2.
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/272 Downloaded from Arrow.com. DS11585 Rev 9 Supply current in Run mode IDD_ALL(Run) fHCLK = fHSE up to 48MHz included, bypass mode PLL ON above 48 MHz all peripherals disable - 0.53 0.30 0.18 0.12 0.06 4 MHz 2 MHz 1 MHz 100 kHz 1.93 32 MHz 8 MHz 2.70 48 MHz 1.03 3.21 64 MHz 16 MHz 3.24 72 MHz 1.46 3.59 80 MHz 24 MHz 25 °C fHCLK 0.08 0.13 0.19 0.31 0.54 1.05 1.48 1.96 2.73 3.24 3.27 3.63 55 °C 0.13 0.19 0.25 0.37 0.60 1.10 1.54 2.02 2.79 3.31 3.34 3.
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Downloaded from Arrow.com. fHCLK = fMSI all peripherals disable FLASH in power-down Supply current in low-power run mode IDD_ALL(Run) DS11585 Rev 9 Range 1 78.5 37.4 400 kHz 100 kHz 2 MHz 136 258 16 MHz 1 MHz 3.02 2.07 24 MHz 5.87 3.97 7.82 64 MHz 32 MHz 8.77 72 MHz 48 MHz 0.14 9.71 80 MHz 0.23 100 kHz 0.33 1 MHz 0.93 8 MHz 2 MHz 1.73 16 MHz 0.53 2.72 26 MHz 4 MHz 25 °C fHCLK 1. Guaranteed by characterization results, unless otherwise specified.
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/272 Downloaded from Arrow.com. Parameter - Conditions(1) DS11585 Rev 9 0.23 0.14 0.10 0.06 4 MHz 2 MHz 1 MHz 100 kHz 0.40 8 MHz 1.43 32 MHz 0.74 2.11 48 MHz 16 MHz 2.81 64 MHz 1.09 3.15 72 MHz 24 MHz 3.49 80 MHz 0.07 0.11 0.16 0.25 0.41 0.76 1.10 1.45 2.13 2.84 3.18 3.52 25 °C 55 °C fHCLK 0.13 0.17 0.21 0.30 0.47 0.81 1.16 1.50 2.19 2.89 3.24 3.58 85 °C TYP 0.22 0.26 0.31 0.39 0.57 0.90 1.25 1.60 2.29 2.99 3.33 3.67 0.42 0.46 0.50 0.
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STM32L496xx Electrical characteristics Table 32. Typical current consumption in Run and Low-power run modes, with different codes running from Flash, ART enable (Cache ON Prefetch OFF) Conditions Supply current in Run mode TYP Voltage scaling - Range 2 fHCLK = 26 MHz IDD_ALL (Run) Parameter fHCLK = fHSE up to 48 MHz included, bypass mode PLL ON above 48 MHz all peripherals disable Range 1 fHCLK = 80 MHz Symbol Code 2.65 102 Coremark 2.97 114 Dhrystone 2.1 3.
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Electrical characteristics STM32L496xx Table 34. Typical current consumption in Run, with different codes running from Flash, ART enable (Cache ON Prefetch OFF) and power supplied (by external SMPS (VDD12 = 1.05 V) Conditions(1) IDD_ALL (Run) Parameter Supply current in Run mode - Voltage scaling fHCLK = fHSE up to 48 MHz included, bypass mode PLL ON above 48 MHz all peripherals disable fHCLK = 26 MHz Symbol TYP TYP Unit Code 25 °C Reduced code(2) 1.04 40 Coremark 1.17 45 Dhrystone 2.
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STM32L496xx Electrical characteristics Table 36. Typical current consumption in Run modes, with different codesrunning from Flash, ART disable and power supplied by external SMPS (VDD12 = 1.10 V) Conditions(1) IDD_ALL (Run) Parameter Supply current in Run mode Voltage scaling - fHCLK = fHSE up to 48 MHz included, bypass mode PLL ON above 48 MHz all peripherals disable fHCLK = 80 MHz fHCLK = 26 MHz Symbol TYP Code 25 °C Reduced code(2) 1.34 TYP Unit 25 °C Unit 51 Coremark 1.
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Electrical characteristics STM32L496xx Table 38.
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STM32L496xx Electrical characteristics Table 40. Typical current consumption in Run, with different codesrunning from SRAM1 and power supplied by external SMPS (VDD12 = 1.05 V) Conditions(1) IDD_ALL (Run) Parameter Supply current in Run mode fHCLK = fHSE up to 48 MHz included, bypass mode PLL ON above 48 MHz all peripherals disable TYP Voltage scaling fHCLK = 26 MHz Symbol Code 25 °C Reduced code(2) 1.07 TYP Unit 25 °C Unit 41 Coremark 1.07 Dhrystone 2.1 1.04 41 Fibonacci 0.
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/272 Downloaded from Arrow.com. DS11585 Rev 9 2.15 1.63 2.57 2.34 2.1 1.58 1.11 0.87 0.63 103 74.2 60 53.7 80 MHz 72 MHz 64 MHz Range 1 48 MHz 32 MHz 24 MHz 16 MHz 2 MHz 1 MHz 400 kHz 100 kHz 0.19 84.1 89.8 111 140 0.67 0.91 1.15 2.38 2.62 0.17 0.16 0.21 0.26 0.13 0.18 0.37 0.57 1 MHz 0.23 0.33 8 MHz 2 MHz 0.54 16 MHz 4 MHz 0.79 26 MHz 0.82 25 °C 55 °C fHCLK 100 kHz Range 2 Voltage scaling 1. Guaranteed by characterization results, unless otherwise specified.
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Downloaded from Arrow.com. Supply current in sleep mode, IDD_ALL(Sleep) fHCLK = fHSE up to 48 MHz included, bypass mode pll ON above 48 MHz all peripherals disable - 0.09 0.08 0.84 0.75 0.57 0.40 0.31 0.23 0.14 0.10 0.08 0.07 0.06 72 MHz 64 MHz 48 MHz 32 MHz 24 MHz 16 MHz 8 MHz 4 MHz 2 MHz 1 MHz 100 kHz 0.07 0.11 0.16 0.24 0.33 0.41 0.59 0.77 0.86 0.94 0.92 80 MHz 55 °C 25 °C fHCLK 0.13 0.13 0.15 0.17 0.21 0.29 0.38 0.47 0.64 0.82 0.91 0.99 85 °C TYP 0.22 0.23 0.24 0.
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/272 Downloaded from Arrow.com. - Voltage scaling Supply current =f f in low-power HCLK MSI all peripherals disable sleep mode Parameter 63.5 42.6 31.2 1 MHz 400 kHz 100 kHz 92.7 2 MHz IDD_ALL (Stop 2) Symbol Supply current in Stop 2 mode, RTC disabled Parameter Conditions DS11585 Rev 9 LCD enabled(2) clocked by LSI LCD disabled - 199 207 223 258 85 °C TYP 437 443 460 487 905 947 951 968 2.92 2.99 3.04 3.31 1.8 V 2.4 V 3V 3.6 V 2.69 3V 2.7 2.62 2.4 V 3.6 V 2.57 1.
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Downloaded from Arrow.com. Parameter Supply current in IDD_ALL(Stop 2 Stop 2 mode, with RTC) RTC enabled Symbol 2.97 3.09 3.15 3.4 2.98 3.10 3.23 1.8 V 2.4 V 3V 3.6 V 1.8 V 2.4 V 3V DS11585 Rev 9 7.81 3.1 3.3 3.48 2.86 3.01 3.18 3.31 RTC clocked by LSE 2.4 V bypassed at 32768Hz,LCD disabled 3 V 3.6 V 1.8 V 2.4 V 3V 3.6 V RTC clocked by LSE quartz(3) in low drive mode, LCD disabled 7.68 2.93 1.8 V 7.94 7.65 7.56 7.48 8.07 7.52 3.47 7.95 7.63 7.46 7.31 8.05 7.81 7.61 7.
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/272 Downloaded from Arrow.com. Parameter 3V 3V 3V Wakeup clock is MSI = 4 MHz, voltage Range 2. See (4). Wakeup clock is HSI16 = 16 MHz, voltage Range 1. See (4). VDD Wakeup clock is MSI = 48 MHz, voltage Range 1. See (4). - 1.7 1.35 1.69 - - - 25 °C 55 °C - - - 85 °C TYP - - - - - - - - - 105 °C 125 °C 25 °C - - - 55 °C 4. Wakeup with code execution from Flash. Average value given for a typical wakeup time as specified in Table 51: Low-power mode wakeup timings.
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Downloaded from Arrow.com. Supply current in Stop 1 mode, RTC disabled IDD_ALL (Stop 1) RTC clocked by LSI - - - DS11585 Rev 9 RTC clocked by LSE quartz(3) in low drive mode LCD disabled LCD disabled LCD enabled(2) LCD disabled LCD enabled(2) clocked by LSI LCD disabled - Conditions Supply current IDD_ALL in stop 1 (Stop 1 with mode, RTC) RTC enabled RTC clocked by LSE bypassed at 32768 Hz Parameter Symbol 31.6 31.9 31.4 31.7 11.8 11.8 12.3 11.6 11.8 12.3 12.7 11.5 11.5 12 12.4 3.
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/272 Downloaded from Arrow.com. Parameter - Wakeup clock MSI = 48 MHz, voltage Range 1. See (4). - Conditions MAX(1) 1.1 0.95 3V 0.99 - - - - - - - - - - - - - - - - - - DS11585 Rev 9 Supply current in Stop 0 mode, RTC disabled IDD_ALL (Stop 0) 129 131 133 2.4 V 3V 3.6 V 127 1.8 V 2. Guaranteed by test in production. 158 156 155 153 25 °C 55 °C VDD 1. Guaranteed by characterization results, unless otherwise specified.
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Downloaded from Arrow.com. IDD_ALL (Standby) IDD_ALL (Standby with RTC) Supply current in Standby mode (backup registers retained), RTC disabled Supply current in Standby mode (backup registers retained), RTC enabled Parameter Symbol 349 411 506 377 461 2.4 V 3V 3.6 V 1.8 V RTC clocked by LSI, no 2.4 V independent watchdog 3V RTC clocked by LSI, with independent watchdog DS11585 Rev 9 518 560 780 3V 3.6 V 422 1.8 V 2.4 V 689 3.6 V 559 296 1.8 V with independent watchdog 171 3.
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/272 Downloaded from Arrow.com. IDD_ALL (Standby with RTC) DS11585 Rev 9 Wakeup clock is MSI = 4 MHz. See (5). - RTC clocked by LSE quartz (3) in low drive mode RTC clocked by LSE bypassed at 32768Hz - 378 3.
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DS11585 Rev 9 Downloaded from Arrow.com. Supply current in Shutdown mode (backup registers retained) RTC disabled Supply current in Shutdown mode (backup registers retained) RTC enabled IDD_ALL (Shutdown) IDD_ALL (Shutdown with RTC) Wakeup clock is MSI = 4 MHz. See (3). RTC clocked by LSE quartz (2) in low drive mode RTC clocked by LSE bypassed at 32768 Hz - - Conditions 421 3V 716 3.
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/272 Downloaded from Arrow.com. Parameter RTC disabled - 375 488 320 3V 3.6 V 1.8 V 648 280 2.4 V 3.6 V 198 1.8 V 512 10 3.6 V 3V 3 3V 405 2 2.4 V 2.
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STM32L496xx Electrical characteristics I/O system current consumption The current consumption of the I/O system has two components: static and dynamic. I/O static current consumption All the I/Os used as inputs with pull-up generate current consumption when the pin is externally held low. The value of this current consumption can be simply computed by using the pull-up/pull-down resistors values given in Table 70: I/O static characteristics.
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Electrical characteristics STM32L496xx On-chip peripheral current consumption The current consumption of the on-chip peripherals is given in Table 50.
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STM32L496xx Electrical characteristics Table 50. Peripheral current consumption (continued) Range 1 Range 2 Low-power run and sleep RNG independent clock domain 2.20 NA NA RNG AHB clock domain 0.51 NA NA SRAM1 2.80 2.29 2.50 SRAM2 1.20 1.00 1.00 TSC 1.50 1.17 1.00 121.00 79.10 87.20 AHB to APB1 bridge(3) 0.90 0.70 0.90 CAN1 3.68 3.04 3.50 DAC1 3.20 2.70 3.00 I2C1 independent clock domain 3.80 3.20 3.30 I2C1 APB clock domain 1.00 0.79 1.
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Electrical characteristics STM32L496xx Table 50. Peripheral current consumption (continued) Range 1 Range 2 Low-power run and sleep TIM2 5.85 4.88 5.70 TIM3 5.20 4.25 5.00 TIM4 4.50 3.67 4.20 TIM5 5.60 4.58 5.10 TIM6 0.85 0.70 0.90 TIM7 0.86 0.71 0.90 USART2 independent clock domain 4.06 3.40 4.00 USART2 APB clock domain 1.38 1.17 1.40 USART3 independent clock domain 4.80 3.92 4.60 USART3 APB clock domain 1.80 1.50 1.80 UART4 independent clock domain 3.80 3.
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STM32L496xx Electrical characteristics Table 50. Peripheral current consumption (continued) Peripheral APB2 All APB2 on ALL Range 1 Range 2 Low-power run and sleep 55.40 41.33 46.00 234.98 195.83 235.70 Unit µA/MHz 1. The BusMatrix is automatically active when at least one master is ON (CPU, DMA). 2.
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Electrical characteristics STM32L496xx Table 51.
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STM32L496xx Electrical characteristics Table 52. Regulator modes transition times(1) Symbol Parameter tWULPRUN tVOST Conditions Typ Max Wakeup time from Low-power run mode to Code run with MSI 2 MHz Run mode(2) 5 7 Regulator transition time from Range 2 to Range 1 or Range 1 to Range 2(3) 20 40 Typ Max Stop 0 mode - 1.7 Stop 1 mode and Stop 2 mode - 8.5 Unit µs Code run with MSI 24 MHz 1. Guaranteed by characterization results. 2. Time until REGLPF flag is cleared in PWR_SR2. 3.
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Electrical characteristics STM32L496xx Figure 23. High-speed external clock source AC timing diagram WZ +6(+ 9+6(+ 9+6(/ WU +6( WI +6( W WZ +6(/ 7+6( 06 9 Low-speed external user clock generated from an external source In bypass mode the LSE oscillator is switched off and the input pin is a standard GPIO. The external clock signal has to respect the I/O characteristics in Section 6.3.14. However, the recommended clock input waveform is shown in Figure 24. Table 55.
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STM32L496xx Electrical characteristics High-speed external clock generated from a crystal/ceramic resonator The high-speed external (HSE) clock can be supplied with a 4 to 48 MHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on design simulation results obtained with typical external components specified in Table 56.
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Electrical characteristics Note: STM32L496xx For information on selecting the crystal, refer to the application note AN2867 “Oscillator design guide for ST microcontrollers” available from the ST website www.st.com. Figure 25. Typical application with an 8 MHz crystal 5HVRQDWRU ZLWK LQWHJUDWHG FDSDFLWRUV &/ 26&B,1 0+] UHVRQDWRU &/ 5(;7 I+6( 5) %LDV FRQWUROOHG JDLQ 26&B287 06 9 1. REXT value depends on the crystal characteristics.
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STM32L496xx Electrical characteristics 1. Guaranteed by design. 2. Refer to the note and caution paragraphs below the table, and to the application note AN2867 “Oscillator design guide for ST microcontrollers”. 3. tSU(LSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 kHz oscillation is reached.
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Electrical characteristics 6.3.8 STM32L496xx Internal clock source characteristics The parameters given in Table 58 are derived from tests performed under ambient temperature and supply voltage conditions summarized in Table 22: General operating conditions. The provided curves are characterization results, not tested in production. High-speed internal (HSI16) RC oscillator Table 58.
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STM32L496xx Electrical characteristics Figure 27. HSI16 frequency versus temperature 0+] 0HDQ PLQ & PD[ 06Y 9 DS11585 Rev 9 159/272 243 Downloaded from Arrow.com.
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Electrical characteristics STM32L496xx Multi-speed internal (MSI) RC oscillator Table 59. MSI oscillator characteristics(1) Symbol Parameter Conditions Min Typ Max Range 0 98.7 100 101.3 Range 1 197.4 200 202.6 Range 2 394.8 400 405.2 Range 3 7896 800 810.4 Range 4 0.987 1 1.013 Range 5 1.974 2 2.026 Range 6 3.948 4 4.052 Range 7 7.896 8 8.104 Range 8 15.79 16 16.21 Range 9 23.69 24 24.31 Range 10 31.58 32 32.42 Range 11 47.38 48 48.62 Range 0 - 98.
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STM32L496xx Electrical characteristics Table 59. MSI oscillator characteristics(1) (continued) Symbol Parameter Conditions Min Typ VDD=1.62 V to 3.6 V -1.2 - VDD=2.4 V to 3.6 V -0.5 - VDD=1.62 V to 3.6 V -2.5 - VDD=2.4 V to 3.6 V -0.8 - VDD=1.62 V to 3.6 V -5 - VDD=2.4 V to 3.6 V -1.
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Electrical characteristics STM32L496xx Table 59. MSI oscillator characteristics(1) (continued) Symbol IDD(MSI)(4) Parameter MSI oscillator power consumption Conditions MSI and PLL mode Min Typ Max Range 0 - - 0.6 1 Range 1 - - 0.8 1.2 Range 2 - - 1.2 1.7 Range 3 - - 1.9 2.5 Range 4 - - 4.7 6 Range 5 - - 6.5 9 Range 6 - - 11 15 Range 7 - - 18.5 25 Range 8 - - 62 80 Range 9 - - 85 110 Range 10 - - 110 130 Range 11 - - 155 190 1.
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STM32L496xx Electrical characteristics High-speed internal 48 MHz (HSI48) RC oscillator Table 60. HSI48 oscillator characteristics(1) Symbol fHSI48 TRIM USER TRIM COVERAGE Parameter Conditions HSI48 Frequency VDD=3.0V, TA=30°C HSI48 user trimming step - HSI48 user trimming coverage ±32 steps DuCy(HSI48) Duty Cycle VDD = 3.0 V to 3.
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Electrical characteristics STM32L496xx Figure 29. HSI48 frequency versus temperature $YJ PLQ & PD[ 06Y 9 Low-speed internal (LSI) RC oscillator Table 61. LSI oscillator characteristics(1) Symbol Parameter LSI Frequency fLSI Min Typ Max VDD = 3.0 V, TA = 30 °C 31.04 - 32.96 VDD = 1.62 to 3.6 V, TA = -40 to 125 °C 29.
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STM32L496xx Electrical characteristics Table 62. PLL, PLLSAI1, PLLSAI2 characteristics(1) (continued) Symbol Parameter Conditions fPLL_P_OUT PLL multiplier output clock P fPLL_Q_OUT PLL multiplier output clock Q fPLL_R_OUT PLL multiplier output clock R fVCO_OUT tLOCK Jitter IDD(PLL) PLL VCO output Min Typ Max Voltage scaling Range 1 2.0645 - 80 Voltage scaling Range 2 2.
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Electrical characteristics STM32L496xx Table 63. Flash memory characteristics(1) (continued) Symbol IDD Parameter Conditions Average consumption from VDD Maximum current (peak) Typ Max Write mode 3.4 - Erase mode 3.4 - Write mode 7 (for 2 μs) - Erase mode 7 (for 41 μs) - Unit mA 1. Guaranteed by design. Table 64.
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STM32L496xx 6.3.11 Electrical characteristics EMC characteristics Susceptibility tests are performed on a sample basis during device characterization. Functional EMS (electromagnetic susceptibility) While a simple application is executed on the device (toggling 2 LEDs through I/O ports). the device is stressed by two electromagnetic events until a failure occurs.
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Electrical characteristics STM32L496xx Prequalification trials Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1 second. To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015).
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STM32L496xx Electrical characteristics Static latch-up Two complementary static tests are required on six parts to assess the latch-up performance: • A supply overvoltage is applied to each power supply pin. • A current injection is applied to each input, output and configurable I/O pin. These tests are compliant with EIA/JESD 78A IC latch-up standard. Table 68. Electrical sensitivities Symbol LU Parameter Static latch-up class Conditions Class TA = +105 °C conforming to JESD78A II level A(1) 1.
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Electrical characteristics 6.3.14 STM32L496xx I/O port characteristics General input/output characteristics Unless otherwise specified, the parameters given in Table 70 are derived from tests performed under the conditions summarized in Table 22: General operating conditions. All I/Os are designed as CMOS- and TTL-compliant (except BOOT0). Table 70. I/O static characteristics Symbol VIL(1) VIH(1) Parameter Conditions 170/272 Downloaded from Arrow.com.
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STM32L496xx Electrical characteristics Table 70. I/O static characteristics (continued) Symbol Parameter Conditions Min Typ Max - - ±100 Max(VDDXXX) ≤ VIN ≤ Max(VDDXXX)+1 V(6)(7) - - 650 Max(VDDXXX)+1 V < VIN ≤ 5.5 V(6)(7) - - 200 VIN ≤ Max(VDDXXX) (6)(7) - - ±150 - - 2500(3) VIN ≤ Max(VDDXXX) FT_xx input leakage current(3)(5) Ilkg (4) (6)(7) Max(VDDXXX) ≤ VIN ≤ FT_lu, FT_u, PB2 and Max(VDDXXX)+1 V(6)(7) PC3 IO Max(VDDXXX)+1 V < VIN ≤ 5.
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Electrical characteristics STM32L496xx All I/Os are CMOS- and TTL-compliant (no software configuration required). Their characteristics cover more than the strict CMOS-technology or TTL parameters. The coverage of these requirements is shown in Figure 30 for standard I/Os, and in Figure 30 for 5 V tolerant I/Os. Figure 30.
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STM32L496xx Electrical characteristics Output voltage levels Unless otherwise specified, the parameters given in the table below are derived from tests performed under the ambient temperature and supply voltage conditions summarized in Table 22: General operating conditions. All I/Os are CMOS- and TTL-compliant (FT OR TT unless otherwise specified). Table 71. Output voltage characteristics(1) Symbol VOL VOH Parameter Conditions Min Max - 0.4 VDDIOx-0.4 - - 0.4 2.4 - - 1.3 VDDIOx-1.
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Electrical characteristics STM32L496xx Table 72. I/O AC characteristics(1)(2) Speed Symbol Fmax Parameter Maximum frequency 00 Tr/Tf Fmax Output rise and fall time Maximum frequency 01 Tr/Tf 174/272 Downloaded from Arrow.com. Output rise and fall time Conditions Min Max C=50 pF, 2.7 V≤VDDIOx≤3.6 V - 5 C=50 pF, 1.62 V≤VDDIOx≤2.7 V - 1 C=50 pF, 1.08 V≤VDDIOx≤1.62 V - 0.1 C=10 pF, 2.7 V≤VDDIOx≤3.6 V - 10 C=10 pF, 1.62 V≤VDDIOx≤2.7 V - 1.5 C=10 pF, 1.08 V≤VDDIOx≤1.62 V - 0.
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STM32L496xx Electrical characteristics Table 72. I/O AC characteristics(1)(2) (continued) Speed Symbol Fmax Parameter Maximum frequency 10 Tr/Tf Fmax Output rise and fall time Maximum frequency 11 Tr/Tf Fm+ Fmax Tf Output rise and fall time Maximum frequency (4) Output fall time Conditions Min Max C=50 pF, 2.7 V≤VDDIOx≤3.6 V - 50 C=50 pF, 1.62 V≤VDDIOx≤2.7 V - 25 C=50 pF, 1.08 V≤VDDIOx≤1.62 V - 5 C=10 pF, 2.7 V≤VDDIOx≤3.6 V - 100(3) C=10 pF, 1.62 V≤VDDIOx≤2.7 V - 37.
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Electrical characteristics STM32L496xx Figure 31. I/O AC characteristics definition(1) W I ,2 RXW W U ,2 RXW 7 0D[LPXP IUHTXHQF\ LV DFKLHYHG LI W W U I 7 DQG LI WKH GXW\ F\FOH LV ZKHQ ORDGHG E\ WKH VSHFLILHG FDSDFLWDQFH 06 9 1. Refer to Table 72: I/O AC characteristics. 6.3.15 NRST pin characteristics The NRST pin input driver uses the CMOS technology. It is connected to a permanent pullup resistor, RPU.
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STM32L496xx Electrical characteristics Figure 32. Recommended NRST pin protection ([WHUQDO UHVHW FLUFXLW 9'' 538 1567 ,QWHUQDO UHVHW )LOWHU ) 06 9 1. The reset network protects the device against parasitic resets. 2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in Table 73: NRST pin characteristics. Otherwise the reset will not be taken into account by the device. 3.
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Electrical characteristics 6.3.18 STM32L496xx Analog-to-Digital converter characteristics Unless otherwise specified, the parameters given in Table 76 are preliminary values derived from tests performed under ambient temperature, fPCLK frequency and VDDA supply voltage conditions summarized in Table 22: General operating conditions. Note: It is recommended to perform a calibration after each power-up. Table 76.
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STM32L496xx Electrical characteristics Table 76. ADC characteristics(1) (2) (continued) Symbol Parameter Conditions Min Typ Max 2.5 3 3.5 - - 3.0 - - 3.25 - - 3.125 0.03125 - 8.00625 µs - 2.5 - 640.5 1/fADC - - - 20 µs 0.1875 - 8.
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Electrical characteristics STM32L496xx Table 77. Maximum ADC RAIN(1)(2) Resolution 12 bits 10 bits 8 bits 6 bits Sampling cycle @80 MHz Sampling time [ns] @80 MHz 2.5 Fast channels(3) Slow channels(4) 31.25 100 N/A 6.5 81.25 330 100 12.5 156.25 680 470 24.5 306.25 1500 1200 47.5 593.75 2200 1800 92.5 1156.25 4700 3900 247.5 3093.75 12000 10000 640.5 8006.75 39000 33000 2.5 31.25 120 N/A 6.5 81.25 390 180 12.5 156.25 820 560 24.5 306.25 1500 1200 47.
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STM32L496xx Electrical characteristics 2. The I/O analog switch voltage booster is enable when VDDA < 2.4 V (BOOSTEN = 1 in the SYSCFG_CFGR1 when VDDA < 2.4V). It is disable when VDDA ≥ 2.4 V. 3. Fast channels are: PC0, PC1, PC2, PC3, PA0. 4. Slow channels are: all ADC inputs except the fast channels. DS11585 Rev 9 181/272 243 Downloaded from Arrow.com.
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Electrical characteristics STM32L496xx Table 78. ADC accuracy - limited test conditions 1(1)(2)(3) Symbol Parameter ET Total unadjusted error EO Conditions(4) Offset error Single ended Differential Single ended Differential Single ended EG Gain error Differential ED EL Differential linearity ADC clock frequency ≤ error 80 MHz, Sampling rate ≤ 5.
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STM32L496xx Electrical characteristics Table 78. ADC accuracy - limited test conditions 1(1)(2)(3) (continued) Symbol THD Conditions(4) Parameter Total harmonic distortion ADC clock frequency ≤ Single 80 MHz, ended Sampling rate ≤ 5.33 Msps, VDDA = VREF+ = 3 V, Differential TA = 25 °C Min Typ Max Unit Fast channel (max speed) - -74 -73 Slow channel (max speed) - -74 -73 Fast channel (max speed) - -79 -76 Slow channel (max speed) - -79 -76 dB 1. Guaranteed by design. 2.
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Electrical characteristics STM32L496xx Table 79. ADC accuracy - limited test conditions 2(1)(2)(3) Symbol Parameter ET Total unadjusted error EO Conditions(4) Offset error Single ended Differential Single ended Differential Single ended EG Gain error Differential ED EL Differential linearity error ADC clock frequency ≤ 80 MHz, Sampling rate ≤ 5.
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STM32L496xx Electrical characteristics Table 79. ADC accuracy - limited test conditions 2(1)(2)(3) (continued) Symbol THD Conditions(4) Parameter Total harmonic distortion Fast channel (max speed) Single ADC clock frequency ≤ ended Slow channel (max speed) 80 MHz, Sampling rate ≤ 5.33 Msps, Fast channel (max speed) Differential 2 V ≤ VDDA Slow channel (max speed) Min Typ Max Unit - -74 -65 - -74 -67 - -79 -70 - -79 -71 dB 1. Guaranteed by design. 2.
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Electrical characteristics STM32L496xx Table 80. ADC accuracy - limited test conditions 3(1)(2)(3) Symbol Parameter ET Total unadjusted error EO Conditions(4) Offset error Single ended Differential Single ended Differential Single ended EG Gain error Differential ED EL Differential linearity ADC clock frequency ≤ error 80 MHz, Sampling rate ≤ 5.33 Msps, 1.65 V ≤ VDDA = VREF+ ≤ 3.
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STM32L496xx Electrical characteristics Table 80. ADC accuracy - limited test conditions 3(1)(2)(3) (continued) Symbol THD Conditions(4) Parameter Total harmonic distortion ADC clock frequency ≤ Single 80 MHz, ended Sampling rate ≤ 5.33 Msps, 1.65 V ≤ VDDA = VREF+ ≤ Differential 3.6 V, Voltage scaling Range 1 Min Typ Max Unit Fast channel (max speed) - -69 -67 Slow channel (max speed) - -71 -67 Fast channel (max speed) - -72 -71 Slow channel (max speed) - -72 -71 dB 1.
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Electrical characteristics STM32L496xx Table 81. ADC accuracy - limited test conditions 4(1)(2)(3) Symbol Parameter ET Total unadjusted error EO Offset error Conditions(4) Single ended Differential Single ended Differential Single ended EG Gain error Differential ED EL Differential linearity ADC clock frequency ≤ error 26 MHz, 1.65 V ≤ VDDA = VREF+ ≤ 3.
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STM32L496xx Electrical characteristics Table 81. ADC accuracy - limited test conditions 4(1)(2)(3) (continued) Symbol THD Conditions(4) Parameter Total harmonic distortion ADC clock frequency ≤ 26 MHz, 1.65 V ≤ VDDA = VREF+ ≤ 3.6 V, Voltage scaling Range 2 Single ended Differential Min Typ Max Unit Fast channel (max speed) - -71 -69 Slow channel (max speed) - -71 -69 Fast channel (max speed) - -73 -72 Slow channel (max speed) - -73 -72 dB 1. Guaranteed by design. 2.
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Electrical characteristics STM32L496xx Figure 33.
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STM32L496xx 6.3.19 Electrical characteristics Digital-to-Analog converter characteristics Table 82. DAC characteristics(1) Symbol Parameter Analog supply voltage for DAC ON VDDA VREF+ Positive reference voltage Conditions Min Typ DAC output buffer OFF (no resistive load on DAC1_OUTx pin or internal connection) 1.71 - Other modes 1.80 - DAC output buffer OFF (no resistive load on DAC1_OUTx pin or internal connection) 1.71 - Other modes 1.
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Electrical characteristics STM32L496xx Table 82.
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STM32L496xx Electrical characteristics Table 82.
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Electrical characteristics STM32L496xx Table 83. DAC accuracy(1) . Symbol Parameter DNL Differential non linearity (2) - monotonicity 10 bits INL Integral non linearity(3) Offset Offset1 OffsetCal Gain TUE TUECal SNR THD 194/272 Downloaded from Arrow.com.
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STM32L496xx Electrical characteristics Table 83. DAC accuracy(1) (continued) Symbol Parameter SINAD Signal-to-noise and distortion ratio ENOB Effective number of bits Conditions Min Typ Max DAC output buffer ON CL ≤ 50 pF, RL ≥ 5 kΩ, 1 kHz - 70.4 - DAC output buffer OFF CL ≤ 50 pF, no RL, 1 kHz - 71 - DAC output buffer ON CL ≤ 50 pF, RL ≥ 5 kΩ, 1 kHz - 11.4 - DAC output buffer OFF CL ≤ 50 pF, no RL, 1 kHz - Unit dB bits 11.5 - 1. Guaranteed by design. 2.
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Electrical characteristics 6.3.20 STM32L496xx Voltage reference buffer characteristics Table 84. VREFBUF characteristics(1) Symbol Parameter Conditions Normal mode VDDA VREFBUF_ OUT Analog supply voltage Voltage reference output Degraded mode(2) Normal mode Degraded mode(2) Min Typ Max VRS = 0 2.4 - 3.6 VRS = 1 2.8 - 3.6 VRS = 0 1.65 - 2.4 VRS = 1 1.65 - 2.8 2.048 2.049(3) (3) VRS = 0 2.046 VRS = 1 2.498(3) 2.5 2.
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STM32L496xx Electrical characteristics Table 84. VREFBUF characteristics(1) (continued) Symbol Parameter VREFBUF IDDA(VREF consumption BUF) from VDDA Conditions Min Typ Max Iload = 0 µA - 16 25 Iload = 500 µA - 18 30 Iload = 4 mA - 35 50 Unit µA 1. Guaranteed by design, unless otherwise specified. 2. In degraded mode, the voltage reference buffer can not maintain accurately the output voltage which will follow (VDDA drop voltage). 3. Guaranteed by test in production. 4.
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Electrical characteristics 6.3.21 STM32L496xx Comparator characteristics Table 85. COMP characteristics(1) Symbol Conditions Min Typ Max Analog supply voltage - 1.62 - 3.6 Comparator input voltage range - 0 - VDDA V VBG(2) Scaler input voltage - VSC Scaler offset voltage - VDDA VIN IDDA(SCALER) Parameter VREFINT - ±5 ±10 mV BRG_EN=0 (bridge disable) - 200 300 nA BRG_EN=1 (bridge enable) - 0.8 1 µA - 100 200 µs VDDA ≥ 2.7 V - - 5 VDDA < 2.
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STM32L496xx Electrical characteristics Table 85.
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Electrical characteristics STM32L496xx Table 86.
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STM32L496xx Electrical characteristics Table 86.
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Electrical characteristics STM32L496xx Table 86.
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STM32L496xx 6.3.23 Electrical characteristics Temperature sensor characteristics Table 87. TS characteristics Symbol Parameter TL(1) Min Typ Max Unit - ±1 ±2 °C 2.3 2.5 2.7 mV/°C 0.742 0.76 0.
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Electrical characteristics 6.3.25 STM32L496xx LCD controller characteristics The devices embed a built-in step-up converter to provide a constant LCD reference voltage independently from the VDD voltage. An external capacitor Cext must be connected to the VLCD pin to decouple this converter. Table 90. LCD controller characteristics(1) Symbol Parameter Conditions Min Typ Max VLCD LCD external voltage - - 3.6 VLCD0 LCD internal reference voltage 0 - 2.
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STM32L496xx Electrical characteristics Table 90.
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Electrical characteristics STM32L496xx Table 91. DFSDM characteristics(1) (continued) Symbol Parameter twh(CKIN) twl(CKIN) Input clock high and low time tsu th TManchester Conditions Min Typ Max SPI mode (SITP[1:0] = 01), External clock mode (SPICKSEL[1:0] = 0) TCKIN/2-0.
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STM32L496xx Electrical characteristics ')6'0B &.,1,1\ ')6'0B'$7$,1\ 63, WLPLQJ 63,&.6(/ Figure 16: DFSDM timing diagram WZO WZK WU WI 63,&.6(/ WVX WK 6,73 WVX WK 6,73 ')6'0B&.287 63,&.6(/ WZO WU WZK WI 63,&.6(/ ')6'0B'$7$,1\ WVX ')6'0B'$7$,1\ 0DQFKHVWHU WLPLQJ 63, WLPLQJ 63,&.6(/ 63,&.6(/ WK 6,73 WVX WK 6,73 6,73 6,73 5HFRYHUHG FORFN 5HFRYHUHG GDWD 06Y 9 6.3.
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Electrical characteristics STM32L496xx Table 92. TIMx(1) characteristics Symbol tres(TIM) Parameter Timer resolution time Conditions Min Max Unit - 1 - tTIMxCLK fTIMxCLK = 80 MHz 12.5 - ns 0 fTIMxCLK/2 MHz 0 40 MHz TIMx (except TIM2 and TIM5) - 16 TIM2 and TIM5 - 32 - 1 65536 tTIMxCLK fTIMxCLK = 80 MHz 0.0125 819.2 µs - - 65536 × 65536 tTIMxCLK fTIMxCLK = 80 MHz - 53.
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STM32L496xx 6.3.28 Electrical characteristics Communication interfaces characteristics I2C interface characteristics The I2C interface meets the timings requirements of the I2C-bus specification and user manual rev. 03 for: • Standard-mode (Sm): with a bit rate up to 100 kbit/s • Fast-mode (Fm): with a bit rate up to 400 kbit/s • Fast-mode Plus (Fm+): with a bit rate up to 1 Mbit/s.
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Electrical characteristics STM32L496xx SPI characteristics Unless otherwise specified, the parameters given in Table 96 for SPI are derived from tests performed under the ambient temperature, fPCLKx frequency and supply voltage conditions summarized in Table 22: General operating conditions. • Output speed is set to OSPEEDRy[1:0] = 11 • Capacitive load C = 30 pF • Measurement points are done at CMOS levels: 0.5 ₓ VDD Refer to Section 6.3.
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STM32L496xx Electrical characteristics Table 96. SPI characteristics(1) (continued) Symbol Parameter tv(SO) Data output valid time tv(MO) th(SO) Data output hold time th(MO) Conditions Min Typ Max Slave mode 2.7 V < VDD < 3.6 V Voltage Range 1 - 13 15.5 Slave mode 1.71 V < VDD < 3.6 V Voltage Range 1 - 13 26.5 Slave mode 1.71 V < VDD < 3.6 V Voltage Range 2 - 13 30 Slave mode 1.08 V < VDDIO2 < 1.32 V(3) - 26 60 Master mode - 4.5 6 Slave mode 1.71 V < VDD < 3.
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Electrical characteristics STM32L496xx Figure 37. SPI timing diagram - slave mode and CPHA = 1 166 LQSXW WF 6&. WVX 166 WZ 6&.+ WD 62 WZ 6&./ WI 6&. WK 166 6&. LQSXW &3+$ &32/ &3+$ &32/ WY 62 WK 62 )LUVW ELW 287 0,62 RXWSXW WVX 6, 1H[W ELWV 287 WU 6&. WGLV 62 /DVW ELW 287 WK 6, 026, LQSXW )LUVW ELW ,1 1H[W ELWV ,1 /DVW ELW ,1 06Y 9 1. Measurement points are done at CMOS levels: 0.3 VDD and 0.7 VDD. Figure 38. SPI timing diagram - master mode +LJK 166 LQSXW 6&.
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STM32L496xx Electrical characteristics Quad SPI characteristics Unless otherwise specified, the parameters given in Table 97 and Table 98 for Quad SPI are derived from tests performed under the ambient temperature, fAHB frequency and VDD supply voltage conditions summarized in Table 22: General operating conditions, with the following configuration: • Output speed is set to OSPEEDRy[1:0] = 11 • Capacitive load C = 15 or 20 pF • Measurement points are done at CMOS levels: 0.5 ₓ VDD Refer to Section 6.3.
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Electrical characteristics STM32L496xx Table 98. QUADSPI characteristics in DDR mode(1) Symbol FCK 1/t(CK) tw(CKH) tw(CKL) Parameter Quad SPI clock frequency Quad SPI clock high and low time tsf(IN);tsr(IN) Data input setup time thf(IN); thr(IN) Data input hold time tvr(OUT) tvf(OUT) thr(OUT) Conditions Min Typ Max 1.71 V < VDD < 3.6 V, CLOAD = 20 pF Voltage Range 1 - - 40 2 V < VDD < 3.6 V, CLOAD = 20 pF Voltage Range 1 - - 48 1.71 V < VDD < 3.
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STM32L496xx Electrical characteristics Figure 39. Quad SPI timing diagram - SDR mode WU &. &ORFN W &. WZ &.+ WY 287 WZ &./ WI &. WK 287 'DWD RXWSXW ' ' WV ,1 'DWD LQSXW ' WK ,1 ' ' ' 06Y 9 Figure 40. Quad SPI timing diagram - DDR mode WU &. &ORFN 'DWD RXWSXW W &. WYI 287 WZ &.+ WKU 287 ' WYU 287 ' ' WZ &./ WKI 287 ' WVI ,1 WKI ,1 'DWD LQSXW ' ' WI &. ' ' WVU ,1 WKU ,1 ' ' ' ' 06Y 9 DS11585 Rev 9 215/272 243 Downloaded from Arrow.com.
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Electrical characteristics STM32L496xx SAI characteristics Unless otherwise specified, the parameters given in Table 99 for SAI are derived from tests performed under the ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized inTable 22: General operating conditions, with the following configuration: • Output speed is set to OSPEEDRy[1:0] = 10 • Capacitive load C = 30 pF • Measurement points are done at CMOS levels: 0.5 ₓ VDD Refer to Section 6.3.
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STM32L496xx Electrical characteristics Table 99. SAI characteristics(1) (continued) Symbol tv(SD_B_ST) th(SD_B_ST) tv(SD_A_MT) th(SD_A_MT) Parameter Conditions Data output valid time Data output hold time Data output valid time Data output hold time Min Max Slave transmitter (after enable edge) 2.7 V ≤ VDD ≤ 3.6 V - 25 Slave transmitter (after enable edge) 1.71 V ≤ VDD ≤ 3.6 V - 36 Slave transmitter (after enable edge) 1.8 V < VDD <1.
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Electrical characteristics STM32L496xx Figure 42.
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STM32L496xx Electrical characteristics Table 100. SD / MMC dynamic characteristics, VDD=2.7 V to 3.6 V(1) (continued) Symbol Parameter Conditions Min Typ Max Unit CMD, D outputs (referenced to CK) in SD default mode tOVD Output valid default time SD fPP = 25 MHz - 3 5 ns tOHD Output hold default time SD fPP = 25 MHz 0 - - ns 1. Guaranteed by characterization results. Table 101. eMMC dynamic characteristics, VDD = 1.71 V to 1.
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Electrical characteristics STM32L496xx Figure 44. SD default mode #+ T/6$ T/($ $ #-$ OUTPUT AI USB OTG full speed (FS) characteristics The STM32L496xx USB interface is fully compliant with the USB specification version 2.0 and is USB-IF certified (for Full-speed device operation). Table 102. USB OTG DC electrical characteristics Symbol Parameter Conditions Min(1) Typ Max(1) Unit VDDUSB USB OTG full speed transceiver operating voltage - 3.0(2) - 3.
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STM32L496xx Electrical characteristics Figure 45. USB OTG timings – definition of data signal rise and fall time &URVV RYHU SRLQWV 'LIIHUHQWLDO GDWD OLQHV 9&56 966 WI WU DL E Table 103.
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Electrical characteristics STM32L496xx Table 104. USB BCD DC electrical characteristics(1) (continued) Symbol Parameter Conditions Min. Typ. Max. Unit VDAT_REF Data detect voltage - 0.25 - 0.4 V VDP_SRC D+ source voltage - 0.5 - 0.7 V VDM_SRC D- source voltage - 0.5 - 0.7 V IDP_SINK D+ sink current - 25 - 175 μA IDM_SINK D- sink current - 25 - 175 μA 1. Guaranteed by design. CAN (controller area network) interface Refer to Section 6.3.
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STM32L496xx 6.3.29 Electrical characteristics FSMC characteristics Unless otherwise specified, the parameters given in Table 105 to Table 118 for the FMC interface are derived from tests performed under the ambient temperature, fHCLK frequency and VDD supply voltage conditions summarized in Table 22, with the following configuration: • Output speed is set to OSPEEDRy[1:0] = 11 • Capacitive load C = 30 pF • Measurement points are done at CMOS levels: 0.5VDD Refer to Section 6.3.
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Electrical characteristics STM32L496xx Figure 46. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms TW .% &-#?.% TV ./%?.% T W ./% T H .%?./% &-#?./% &-#?.7% TV !?.% &-#?!; = T H !?./% !DDRESS TV ",?.% T H ",?./% &-#?.",; = T H $ATA?.% T SU $ATA?./% TH $ATA?./% T SU $ATA?.% $ATA &-#?$; = T V .!$6?.% TW .!$6 &-#?.!$6 &-#?.7!)4 TH .%?.7!)4 TSU .7!)4?.% -3 6 224/272 Downloaded from Arrow.com.
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STM32L496xx Electrical characteristics Table 105. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings(1)(2) Symbol Min Max 2THCLK-1 2THCLK+1 0 0.5 2THCLK-1 2THCLK+1 FMC_NOE high to FMC_NE high hold time 0 - FMC_NEx low to FMC_A valid - 0.5 th(A_NOE) Address hold time after FMC_NOE high 0 - tv(BL_NE) FMC_NEx low to FMC_BL valid - 0.
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Electrical characteristics STM32L496xx Figure 47. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms TW .% &-#?.%X &-#?./% TV .7%?.% TW .7% T H .%?.7% &-#?.7% TV !?.% &-#?!; = TH !?.7% !DDRESS TV ",?.% &-#?.",; = TH ",?.7% .", TV $ATA?.% TH $ATA?.7% $ATA &-#?$; = T V .!$6?.% &-#?.!$6 TW .!$6 &-#?.7!)4 TH .%?.7!)4 TSU .7!)4?.% -3 6 Table 107.
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STM32L496xx Electrical characteristics Table 108. Asynchronous non-multiplexed SRAM/PSRAM/NOR write-NWAIT timings(1)(2) Symbol Parameter tw(NE) FMC_NE low time tw(NWE) FMC_NWE low time Min Max 8THCLK-1 8THCLK+1 6THCLK-1.5 6THCLK+0.5 tsu(NWAIT_NE) FMC_NWAIT valid before FMC_NEx high 6THCLK-1 - th(NE_NWAIT) FMC_NEx hold time after FMC_NWAIT invalid 4THCLK+2 - Unit ns 1. CL = 30 pF. 2. Guaranteed by characterization results. Figure 48.
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Electrical characteristics STM32L496xx Table 109. Asynchronous multiplexed PSRAM/NOR read timings(1)(2) Symbol Min Max 3THCLK -1 3THCLK+1 2THCLK 2THCLK+0.5 THCLK - 1 THCLK+1 FMC_NOE high to FMC_NE high hold time 0 - FMC_NEx low to FMC_A valid - 0.5 0 0.5 FMC_NADV low time THCLK - 0.5 THCLK+1 th(AD_NADV) FMC_AD(address) valid hold time after FMC_NADV high THCLK + 0.5 - th(A_NOE) Address hold time after FMC_NOE high THCLK - 0.
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STM32L496xx Electrical characteristics Figure 49. Asynchronous multiplexed PSRAM/NOR write waveforms TW .% &-#? .%X &-#?./% TV .7%?.% TW .7% T H .%?.7% &-#?.7% TH !?.7% TV !?.% &-#? !; = !DDRESS TV ",?.% TH ",?.7% &-#? .",; = .", T V !?.% T V $ATA?.!$6 !DDRESS &-#? !$; = TH $ATA?.7% $ATA TH !$?.!$6 T V .!$6?.% TW .!$6 &-#?.!$6 &-#?.7!)4 TH .%?.7!)4 TSU .7!)4?.% -3 6 Table 111.
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Electrical characteristics STM32L496xx 1. CL = 30 pF. 2. Guaranteed by characterization results. Table 112. Asynchronous multiplexed PSRAM/NOR write-NWAIT timings(1)(2) Symbol Min Max 9THCLK- 1 9THCLK+ 1 7THCLK- 0.5 7THCLK+ 0.5 tsu(NWAIT_NE) FMC_NWAIT valid before FMC_NEx high 6THCLK+ 2 - th(NE_NWAIT) 4THCLK- 1 - tw(NE) tw(NWE) Parameter FMC_NE low time FMC_NWE low time FMC_NEx hold time after FMC_NWAIT invalid Unit ns 1. CL = 30 pF. 2. Guaranteed by characterization results.
PAGE 231
STM32L496xx Electrical characteristics Figure 50. Synchronous multiplexed NOR/PSRAM read timings "53452. TW #,+ TW #,+ &-#?#,+ $ATA LATENCY TD #,+, .%X, &-#?.%X T D #,+, .!$6, TD #,+( .%X( TD #,+, .!$6( &-#?.!$6 TD #,+, !6 TD #,+( !)6 &-#?!; = TD #,+, ./%, TD #,+( ./%( &-#?./% T D #,+, !$6 &-#?!$; = TD #,+, !$)6 TSU !$6 #,+( !$; = TH #,+( !$6 TSU !$6 #,+( $ TSU .7!)46 #,+( &-#?.7!)4 7!)4#&' B 7!)40/, B &-#?.7!)4 7!)4#&' B 7!)40/, B TSU .7!)46 #,+( TSU .
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Electrical characteristics STM32L496xx Table 113. Synchronous multiplexed NOR/PSRAM read timings(1)(2) Symbol Min Max 2THCLK-0.5 - - 2 THCLK+0.5 - td(CLKL-NADVL) FMC_CLK low to FMC_NADV low - 1 td(CLKL-NADVH) FMC_CLK low to FMC_NADV high 0 - - 4.5 THCLK - - 1.5 THCLK+0.5 - tw(CLK) Parameter FMC_CLK period td(CLKL-NExL) FMC_CLK low to FMC_NEx low (x=0..
PAGE 233
STM32L496xx Electrical characteristics Figure 51. Synchronous multiplexed PSRAM write timings WZ &/. %867851 WZ &/. )0&B&/. 'DWD ODWHQF\ WG &/./ 1([/ WG &/.+ 1([+ )0&B1([ WG &/./ 1$'9/ WG &/./ 1$'9+ )0&B1$'9 WG &/.+ $,9 WG &/./ $9 )0&B$> @ WG &/.+ 1:(+ WG &/./ 1:(/ )0&B1:( WG &/./ 'DWD WG &/./ $',9 WG &/./ 'DWD WG &/./ $'9 )0&B$'> @ )0&B1:$,7 :$,7&)* E :$,732/ E $'> @ ' WVX 1:$,79 &/.+ ' WK &/.+ 1:$,79 WG &/.
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Electrical characteristics STM32L496xx Table 114. Synchronous multiplexed PSRAM write timings(1)(2) Symbol tw(CLK) Parameter FMC_CLK period 2THCLK- 0.5 - - 2 THCLK+ 0.5 - FMC_CLK low to FMC_NEx low (x=0..2) td(CLKH-NExH) FMC_CLK high to FMC_NEx high (x= 0…2) td(CLKL-NADVL) FMC_CLK low to FMC_NADV low - 1 td(CLKL-NADVH) FMC_CLK low to FMC_NADV high 0 - td(CLKL-AV) FMC_CLK low to FMC_Ax valid (x=16…25) - 4.5 td(CLKH-AIV) FMC_CLK high to FMC_Ax invalid (x=16…25) THCLK - - 1.
PAGE 235
STM32L496xx Electrical characteristics Figure 52. Synchronous non-multiplexed NOR/PSRAM read timings TW #,+ TW #,+ &-#?#,+ TD #,+, .%X, TD #,+( .%X( $ATA LATENCY &-#?.%X TD #,+, .!$6, TD #,+, .!$6( &-#?.!$6 TD #,+( !)6 TD #,+, !6 &-#?!; = TD #,+, ./%, TD #,+( ./%( &-#?./% TSU $6 #,+( TH #,+( $6 TSU $6 #,+( &-#?$; = TH #,+( $6 $ TSU .7!)46 #,+( &-#?.7!)4 7!)4#&' B 7!)40/, B $ TH #,+( .7!)46 TSU .7!)46 #,+( &-#?.7!)4 7!)4#&' B 7!)40/, B TSU .7!)46 #,+( T H #,+( .
PAGE 236
Electrical characteristics STM32L496xx Table 115. Synchronous non-multiplexed NOR/PSRAM read timings(1)(2) (continued) Symbol Parameter tsu(NWAIT-CLKH) FMC_NWAIT valid before FMC_CLK high th(CLKH-NWAIT) FMC_NWAIT valid after FMC_CLK high Min Max 2 - 3.5 - Unit ns 1. CL = 30 pF. 2. Guaranteed by characterization results. Figure 53. Synchronous non-multiplexed PSRAM write timings WZ &/. WZ &/. )0&B&/. WG &/./ 1([/ WG &/.+ 1([+ 'DWD ODWHQF\ )0&B1([ WG &/./ 1$'9/ WG &/.
PAGE 237
STM32L496xx Electrical characteristics Table 116. Synchronous non-multiplexed PSRAM write timings(1)(2) Symbol tw(CLK) Parameter FMC_CLK period Min Max 2THCLK-0.5 - - 2 THCLK+0.5 - td(CLKL-NExL) FMC_CLK low to FMC_NEx low (x=0..2) td(CLKH-NExH) FMC_CLK high to FMC_NEx high (x= 0…2) td(CLKL-NADVL) FMC_CLK low to FMC_NADV low - 0.
PAGE 238
Electrical characteristics STM32L496xx Figure 54. NAND controller waveforms for read access )0&B1&([ $/( )0&B$ &/( )0&B$ )0&B1:( WK 12( $/( WG 1&( 12( )0&B12( 15( WVX ' 12( WK 12( ' )0&B'> @ 06Y 9 Figure 55. NAND controller waveforms for write access )0&B1&([ $/( )0&B$ &/( )0&B$ WK 1:( $/( WG 1&( 1:( )0&B1:( )0&B12( 15( WK 1:( ' WY 1:( ' )0&B'> @ 06Y 9 Figure 56.
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STM32L496xx Electrical characteristics Figure 57. NAND controller waveforms for common memory write access )0&B1&([ $/( )0&B$ &/( )0&B$ WG 1&( 1:( WZ 1:( WK 12( $/( )0&B1:( )0&B12( WG ' 1:( WY 1:( ' WK 1:( ' )0&B'> @ 06Y 9 Table 117. Switching characteristics for NAND Flash read cycles(1)(2) Symbol Tw(N0E) Parameter FMC_NOE low width Min Max Unit 4THCLK-0.5 4THCLK+0.
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Electrical characteristics STM32L496xx summarized in Table 21, with the following configuration: • DCMI_PIXCLK polarity: falling • DCMI_VSYNC and DCMI_HSYNC polarity: high • Data format: 14 bits • Capacitive load C=30pF Figure 58. DCMI timing diagram '&0,B3,;&/. '&0,B3,;&/. WVX +6<1& WK +6<1& '&0,B+6<1& WVX 96<1& WK +6<1& '&0,B96<1& WVX '$7$ WK '$7$ '$7$> @ 06 9 Table 119. DCMI characteristics(1) Symbol Parameter Min Max Frequency ratio DCMI_PIXCLK/fHCLK - 0.
PAGE 241
STM32L496xx 6.3.31 Electrical characteristics SWPMI characteristics The Single Wire Protocol Master Interface (SWPMI) and the associated SWPMI_IO transceiver are compliant with the ETSI TS 102 613 technical specification. Table 120. SWPMI electrical characteristics Symbol 6.3.32 Parameter Conditions tSWPSTART SWPMI regulator startup time tSWPBIT SWP bit duration Min Typ - - 300 VCORE voltage range 1 500 - - VCORE voltage range 2 620 - - SWP Class B 2.
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Electrical characteristics STM32L496xx Figure 60. SD default mode #+ T/6$ T/($ $ #-$ OUTPUT AI Table 121. SD / MMC dynamic characteristics, VDD=2.7 V to 3.
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STM32L496xx Electrical characteristics Table 122. SD / MMC dynamic characteristics, VDD=1.71 V to 1.9 V(1) (continued) Symbol Parameter Conditions Min Typ Max Unit CMD, D inputs (referenced to CK) in MMC and SD HS mode tISU Input setup time HS fPP = 50 MHz 2.5 - - ns tIH Input hold time HS fPP = 50 MHz 2.5 - - ns CMD, D outputs (referenced to CK) in MMC and SD HS mode tOV Output valid time HS fPP = 50 MHz - 13.5 16.
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Package information 7 STM32L496xx Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. 7.1 UFBGA169 package information Figure 61. UFBGA169 - 169-ball, 7 x 7 mm, 0.
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STM32L496xx Package information Table 123. UFBGA169 - 169-ball, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array package mechanical data (continued) inches(1) millimeters Symbol Min. Typ. Max. Min. Typ. Max. b 0.230 0.280 0.330 0.0091 0.0110 0.0130 D 6.950 7.000 7.050 0.2736 0.2756 0.2776 D1 5.950 6.000 6.050 0.2343 0.2362 0.2382 E 6.950 7.000 7.050 0.2736 0.2756 0.2776 E1 5.950 6.000 6.050 0.2343 0.2362 0.2382 e - 0.500 - - 0.0197 - F 0.450 0.
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Package information Note: STM32L496xx 4 to 6 mils solder paste screen printing process. Device marking The following figure gives an example of topside marking orientation versus ball A1 identifier location. Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. Figure 63. UFBGA169 marking (package top view) 3LQ LGHQWLILHU 3URGXFW LGHQWLILFDWLRQ 670 / $*, < :: 'DWH FRGH $ 06Y 9 1.
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STM32L496xx Package information Figure 64. UFBGA169, external SMPS device, marking (package top view) 3LQ LGHQWLILHU 3URGXFW LGHQWLILFDWLRQ 670 / $*, 3 < :: 'DWH FRGH % 06Y 9 1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use.
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Package information 7.2 STM32L496xx LQFP144 package information Figure 65. LQFP144 - 144-pin, 20 x 20 mm low-profile quad flat package outline 6($7,1* 3/$1( F $ $ $ & PP *$8*( 3/$1( ' / ' . $ FFF & / ' ( 3,1 ( ( E ,'(17,),&$7,21 H $B0(B9 1. Drawing is not to scale. 248/272 Downloaded from Arrow.com.
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STM32L496xx Package information Table 125. LQFP144 - 144-pin, 20 x 20 mm low-profile quad flat package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A - - 1.600 - - 0.0630 A1 0.050 - 0.150 0.0020 - 0.0059 A2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 D 21.800 22.000 22.200 0.8583 0.8661 0.8740 D1 19.800 20.000 20.200 0.7795 0.7874 0.7953 D3 - 17.500 - - 0.
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Package information STM32L496xx Figure 66. LQFP144 - 144-pin,20 x 20 mm low-profile quad flat package recommended footprint DL H 1. Dimensions are expressed in millimeters. 250/272 Downloaded from Arrow.com.
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STM32L496xx Package information Device marking The following figure gives an example of topside marking orientation versus pin 1 identifier location. Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. Figure 67. LQFP144 marking (package top view) 2SWLRQDO JDWH PDUN 5HYLVLRQ FRGH 3URGXFW LGHQWLILFDWLRQ % 670 / =*7 'DWH FRGH < :: 3LQ LGHQWLILHU 06Y 9 1.
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Package information STM32L496xx Figure 68. LQFP144, external SMPS device, marking (package top view) 2SWLRQDO JDWH PDUN 5HYLVLRQ FRGH 3URGXFW LGHQWLILFDWLRQ % 670 / =*7 3 'DWH FRGH < :: 3LQ LGHQWLILHU 06Y 9 1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use.
PAGE 253
STM32L496xx 7.3 Package information UFBGA132 package information Figure 69. UFBGA132 - 132-ball, 7 x 7 mm ultra thin fine pitch ball grid array package outline $ EDOO LGHQWLILHU $ % ( H ( = $ = ' ' H 0 %27720 9,(: E EDOOV HHH 0 & $ % III 0 & 723 9,(: $ GGG & $ $ $ $ E 6($7,1* 3/$1( 8)%*$ B$ * B0(B9 1. Drawing is not to scale. Table 126.
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Package information STM32L496xx Table 126. UFBGA132 - 132-ball, 7 x 7 mm ultra thin fine pitch ball grid array package mechanical data (continued) inches(1) millimeters Symbol Min Typ Max Min Typ Max e - 0.500 - - 0.0197 - Z - 0.750 - - 0.0295 - ddd - 0.080 - - 0.0031 - eee - 0.150 - - 0.0059 - fff - 0.050 - - 0.0020 - 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 70.
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STM32L496xx Package information Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. Figure 71. UFBGA132 marking (package top view) 3URGXFW LGHQWLILFDWLRQ 670 / 4*, < ZZ $ %DOO $ LQGHQWLILHU 'DWH FRGH 5HYLVLRQ FRGH 06Y 9 1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified and therefore not approved for use in production.
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Package information 7.4 STM32L496xx LQFP100 package information Figure 73. LQFP100 - 100-pin, 14 x 14 mm low-profile quad flat package outline MM C ! ! ! 3%!4).' 0,!.% # '!5'% 0,!.% $ ! + CCC # , $ , $ 0). )$%.4)&)#!4)/. % % % B E ,?-%?6 1. Drawing is not to scale. Table 128. LQPF100 - 100-pin, 14 x 14 mm low-profile quad flat package mechanical data inches(1) millimeters Symbol 256/272 Downloaded from Arrow.com.
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STM32L496xx Package information Table 128. LQPF100 - 100-pin, 14 x 14 mm low-profile quad flat package mechanical data (continued) inches(1) millimeters Symbol Min Typ Max Min Typ Max E1 13.800 14.000 14.200 0.5433 0.5512 0.5591 E3 - 12.000 - - 0.4724 - e - 0.500 - - 0.0197 - L 0.450 0.600 0.750 0.0177 0.0236 0.0295 L1 - 1.000 - - 0.0394 - k 0.0° 3.5° 7.0° 0.0° 3.5° 7.0° ccc - - 0.080 - - 0.0031 1.
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Package information STM32L496xx Figure 75. LQFP100 marking (package top view) 3URGXFW LGHQWLILFDWLRQ 670 / 2SWLRQDO JDWH PDUN 9&7 $ 5HYLVLRQ FRGH 'DWH FRGH < ZZ 3LQ LQGHQWLILHU 06Y 9 1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use.
PAGE 259
STM32L496xx 7.5 Package information WLCSP100 package information Figure 76.WLCSP – 100 ball, 4.618 x 4.142 mm, 0.4 mm pitch wafer level chip scale package outline $ 25,(17$7,21 5()(5(1&( H ) * $ H ( H ( . DDD ; H ' ' %27720 9,(: %803 6,'( 723 9,(: :$)(5 %$&. 6,'( %803 $ HHH = = E ; '(7$,/ $ = ; < 6,'( 9,(: = '(7$,/ $ 6($7,1* 3/$1( $ 'B0(B9 1. Drawing is not to scale. 2. Dimension is measured at the maximum bump diameter parallel to primary datum Z. 3.
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Package information STM32L496xx Table 129. WLCSP – 100 ball, 4.618 x 4.142 mm, 0.4 mm pitch wafer level chip scale package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A 0.525 0.555 0.585 0.0207 0.0219 0.0230 A1 - 0.175 - - 0.0069 - A2 - 0.380 - - 0.0150 - (2) - 0.025 - - 0.0010 - (3) Øb 0.220 0.250 0.280 0.0087 0.0098 0.0110 D 4.583 4.618 4.653 0.1804 0.1818 0.1832 E 4.107 4.142 4.177 0.1617 0.1631 0.1644 e - 0.
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STM32L496xx Package information Table 130. WLCSP100 recommended PCB design rules (0.4 mm pitch) Dimension Recommended values Pitch 0.4 mm Dpad 0.225 mm Dsm 0.290 mm Stencil thickness 0.1 mm Figure 78. WLCSP100 marking (package top view) 3LQ LQGHQWLILHU 3URGXFW LGHQWLILFDWLRQ / 9*< < ZZ $ 'DWH FRGH H 06Y 9 1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified and therefore not approved for use in production.
PAGE 262
Package information STM32L496xx Figure 79. WLCSP100, external SMPS device, marking (package top view) 3LQ LQGHQWLILHU 3URGXFW LGHQWLILFDWLRQ / 9*3 < ZZ % 'DWH FRGH H 06Y 9 1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use.
PAGE 263
STM32L496xx 7.6 Package information LQFP64 package information Figure 80. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package outline PP *$8*( 3/$1( F $ $ $ 6($7,1* 3/$1( & $ FFF & ' ' ' . / / 3,1 ,'(17,),&$7,21 ( ( ( E H :B0(B9 1. Drawing is not to scale. Table 131. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A - - 1.600 - - 0.0630 A1 0.
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Package information STM32L496xx Table 131. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package mechanical data (continued) inches(1) millimeters Symbol Min Typ Max Min Typ Max E3 - 7.500 - - 0.2953 - e - 0.500 - - 0.0197 - K 0° 3.5° 7° 0° 3.5° 7° L 0.450 0.600 0.750 0.0177 0.0236 0.0295 L1 - 1.000 - - 0.0394 - ccc - - 0.080 - - 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 81.
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STM32L496xx Package information Figure 82. LQFP64 marking (package top view) 5HYLVLRQ FRGH $ 3URGXFW LGHQWLILFDWLRQ 670 / 5&7 < :: 'DWH FRGH 3LQ LGHQWLILHU 06Y 9 1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use.
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Package information 7.7 STM32L496xx Thermal characteristics The maximum chip-junction temperature, TJ max, in degrees Celsius, may be calculated using the following equation: TJ max = TA max + (PD max x ΘJA) Where: • TA max is the maximum ambient temperature in °C, • ΘJA is the package junction-to-ambient thermal resistance, in °C/W, • PD max is the sum of PINT max and PI/O max (PD max = PINT max + PI/Omax), • PINT max is the product of all IDDXXX and VDDXXX, expressed in Watts.
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STM32L496xx Package information The following examples show how to calculate the temperature range needed for a given application. Example 1: High-performance application Assuming the following application conditions: Maximum ambient temperature TAmax = 82 °C (measured according to JESD51-2), IDDmax = 50 mA, VDD = 3.5 V, maximum 20 I/Os used at the same time in output at low level with IOL = 8 mA, VOL= 0.4 V and maximum 8 I/Os used at the same time in output at low level with IOL = 20 mA, VOL= 1.
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Package information STM32L496xx In this case, parts must be ordered at least with the temperature range suffix 3 (see Section 8: Ordering information) unless we reduce the power dissipation in order to be able to use suffix 6 parts. 268/272 Downloaded from Arrow.com.
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STM32L496xx 8 Ordering information Ordering information Table 133.
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Revision history 9 STM32L496xx Revision history Table 134. Document revision history Date Revision 22-Feb-2017 1 Initial release. 2 Updated: – Features in cover page, Section 2: Description, Section 6.1.7: Current consumption measurement, Section 6.3.18: Analog-to-Digital converter characteristics, Section 7.7: Thermal characteristics, Section 7.7.
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STM32L496xx Revision history Table 134. Document revision history (continued) Date 15-May-2018 16-Jul-2018 Revision Changes 8 Updated: Figure 1: STM32L496xx block diagram, Figure 5: Clock tree, Section 3.10.1: Power supply schemes, Table 5: Functionalities depending on the working mode, , Table 19: Voltage characteristics, Table 18: STM32L496xx memory map and peripheral register boundary addresses, Section 3.17: Analog to digital converter (ADC), Section 6.3.
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STM32L496xx IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.