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STM32L486xx Functional overview

without having any impact on the timing of “injected” conversions

– “injected” conversions for precise timing and with high conversion priority

3.23 Random number generator (RNG)

All devices embed an RNG that delivers 32-bit random numbers generated by an integrated

analog circuit.

3.24 Advanced encryption standard hardware accelerator (AES)

The devices embed an AES hardware accelerator can be used to both encipher and

decipher data using AES algorithm.

The AES peripheral supports:

• Encryption/Decryption using AES Rijndael Block Cipher algorithm

• NIST FIPS 197 compliant implementation of AES encryption/decryption algorithm

• 128-bit and 256-bit register for storing the encryption, decryption or derivation key (4x

32-bit registers)

• Electronic codebook (ECB), Cipher block chaining (CBC), Counter mode (CTR), Galois

Counter Mode (GCM), Galois Message Authentication Code mode (GMAC) and Cipher

Message Authentication Code mode (CMAC) supported.

• Key scheduler

• Key derivation for decryption

• 128-bit data block processing

• 128-bit, 256-bit key length

• 1x32-bit INPUT buffer and 1x32-bit OUTPUT buffer.

• Register access supporting 32-bit data width only.

• One 128-bit Register for the initialization vector when AES is configured in CBC mode

or for the 32-bit counter initialization when CTR mode is selected, GCM mode or

CMAC mode.

• Automatic data flow control with support of direct memory access (DMA) using 2

channels, one for incoming data, and one for outcoming data.

• Suspend a message if another message with a higher priority needs to be processed

Table 10. DFSDM1 implementation

DFSDM features DFSDM1

Number of channels 8

Number of filters 4

Input from internal ADC -

Supported trigger sources 10

Pulses skipper -

ID registers support -

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