Datasheet

Functional overview STM32L475xx
24/204 DS10969 Rev 5
Stop 1 LPR No Off ON
LSE
LSI
BOR, PVD, PVM
RTC, IWDG
COMPx (x=1,2)
DAC1
OPAMPx (x=1,2)
USARTx (x=1...5)
(6)
LPUART1
(6)
I2Cx (x=1...3)
(7)
LPTIMx (x=1,2)
***
All other peripherals are
frozen.
Reset pin, all I/Os
BOR, PVD, PVM
RTC, IWDG
COMPx (x=1..2)
USARTx (x=1...5)
(6)
LPUART1
(6)
I2Cx (x=1...3)
(7)
LPTIMx (x=1,2)
OTG_FS
(8)
SWPMI1
(9)
6.6 µA w/o RTC
6.9 µA w RTC
4 µs in SRAM
6 µs in Flash
Stop 2 LPR No Off ON
LSE
LSI
BOR, PVD, PVM
RTC, IWDG
COMPx (x=1..2)
I2C3
(7)
LPUART1
(6)
LPTIM1
***
All other peripherals are
frozen.
Reset pin, all I/Os
BOR, PVD, PVM
RTC, IWDG
COMPx (x=1..2)
I2C3
(7)
LPUART1
(6)
LPTIM1
1.1 µA w/o RTC
1.4 µA w/RTC
5 µs in SRAM
7 µs in Flash
Table 4. STM32L475xx modes overview (continued)
Mode
Regulator
(1)
CPU Flash SRAM Clocks DMA & Peripherals
(2)
Wakeup source Consumption
(3)
Wakeup time
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