Datasheet

STM32L475xx Functional overview
DS10969 Rev 5 23/204
Table 4. STM32L475xx modes overview
Mode
Regulator
(1)
CPU Flash SRAM Clocks DMA & Peripherals
(2)
Wakeup source Consumption
(3)
Wakeup time
Run
Range 1
Yes ON
(4)
ON Any
All
N/A
112 µA/MHz
N/A
Range2 All except OTG_FS, RNG 100 µA/MHz
LPRun LPR Yes ON
(4)
ON
Any
except
PLL
All except OTG_FS, RNG N/A 136 µA/MHz
to Range 1: 4 µs
to Range 2: 64 µs
Sleep
Range 1
No ON
(4)
ON
(5)
Any
All
Any interrupt or
event
37 µA/MHz 6 cycles
Range 2 All except OTG_FS, RNG 35 µA/MHz 6 cycles
LPSleep LPR No ON
(4)
ON
(5)
Any
except
PLL
All except OTG_FS, RNG
Any interrupt or
event
40 µA/MHz 6 cycles
Stop 0
Range 1
No Off ON
LSE
LSI
BOR, PVD, PVM
RTC, IWDG
COMPx (x=1,2)
DAC1
OPAMPx (x=1,2)
USARTx (x=1...5)
(6)
LPUART1
(6)
I2Cx (x=1...3)
(7)
LPTIMx (x=1,2)
***
All other peripherals are
frozen.
Reset pin, all I/Os
BOR, PVD, PVM
RTC, IWDG
COMPx (x=1..2)
USARTx (x=1...5)
(6)
LPUART1
(6)
I2Cx (x=1...3)
(7)
LPTIMx (x=1,2)
OTG_FS
(8)
SWPMI1
(9)
108 µA
0.7 µs in SRAM
4.5 µs in Flash
Range 2
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