Datasheet

Electrical characteristics STM32L475xx
174/204 DS10969 Rev 5
Figure 29. Quad SPI timing diagram - SDR mode
Figure 30. Quad SPI timing diagram - DDR mode
Table 87. QUADSPI characteristics in DDR mode
(1)
Symbol Parameter Conditions Min Typ Max Unit
F
CK
1/t
(CK)
Quad SPI clock
frequency
1.71 < V
DD
< 3.6 V, C
LOAD
= 20 pF
Voltage Range 1
--40
MHz
2 < V
DD
< 3.6 V, C
LOAD
= 20 pF
Voltage Range 1
--48
1.71 < V
DD
< 3.6 V, C
LOAD
= 15 pF
Voltage Range 1
--48
1.71 < V
DD
< 3.6 V C
LOAD
= 20 pF
Voltage Range 2
--26
t
w(CKH)
Quad SPI clock high
and low time
f
AHBCLK
= 48 MHz, presc=0
t
(CK)
/2-2 - t
(CK)
/2
ns
t
w(CKL)
t
(CK)
/2 - t
(CK)
/2+2
t
sf(IN)
;t
sr(IN)
Data input setup time
Voltage Range 1 and 2
3.5 - -
t
hf(IN)
; t
hr(IN)
Data input hold time 6.5 - -
t
vf(OUT)
;t
vr(OUT)
Data output valid time
Voltage Range 1
-
11 12
Voltage Range 2 15 19
t
hf(OUT)
; t
hr(OUT)
Data output hold time
Voltage Range 1 6 -
-
Voltage Range 2 8 -
1. Guaranteed by characterization results.
MSv36878V1
Data output
D0
D1 D2
Clock
Data input
D0 D1 D2
t
(CK)
t
w(CKH)
t
w(CKL)
t
r(CK)
t
f(CK)
t
s(IN)
t
h(IN)
t
v(OUT)
t
h(OUT)
MSv36879V1
Data output
D0
D2 D4
Clock
Data input
D0 D2 D4
t
(CK)
t
w(CKH)
t
w(CKL)
t
r(CK)
t
f(CK)
t
sf(IN)
t
hf(IN)
t
vf(OUT)
t
hr(OUT)
D1 D3 D5
D1 D3 D5
t
vr(OUT)
t
hf(OUT)
t
sr(IN)
t
hr(IN)
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