Datasheet

DS10969 Rev 5 133/204
STM32L475xx Electrical characteristics
190
I
lkg
(4)
FT_xx input leakage
current
(3)(5)
V
IN

Max(V
DDXXX
)
(6)(7)
- - ±100
nA
Max(V
DDXXX
)  V
IN

Max(V
DDXXX
)+1 V
(6)(7)
--650
Max(V
DDXXX
)+1 V <
V
IN
 5.5 V
(6)(7)
--200
FT_u and PC3 I/O
V
IN

Max(V
DDXXX
)
(6)(7)
- - ±150
Max(V
DDXXX
)  V
IN

Max(V
DDXXX
)+1 V
(6)(7)
- - 2500
(3)
Max(V
DDXXX
)+1 V <
V
IN
 5.5 V
(6)(7)
--250
TT_xx input leakage
current
V
IN
 Max(V
DDXXX
)
(6)
- - ±150
Max(V
DDXXX
)  V
IN
<
3.6 V
(6)
- - 2000
(3)
R
PU
Weak pull-up
equivalent resistor
(8)
V
IN
= V
SS
25 40 55 k
R
PD
Weak pull-down
equivalent resistor
(8)
V
IN
= V
DDIOx
25 40 55 k
C
IO
I/O pin capacitance - - 5 - pF
1. Refer to Figure 20: I/O input characteristics.
2. Guaranteed by test in production.
3. Guaranteed by design.
4. This value represents the pad leakage of the IO itself. The total product pad leakage is provided by this formula:
I
Total_Ileak_max
= 10 µA + [number of IOs where V
IN
is applied on the pad]  I
lkg
(Max).
5. All FT_xx GPIOs except FT_u and PC3.
6. Max(V
DDXXX
) is the maximum value of all the I/O supplies. Refer to Table: Legend/Abbreviations used in the pinout table.
7. To sustain a voltage higher than Min(V
DD
, V
DDA
, V
DDUSB
) +0.3 V, the internal Pull-up and Pull-Down resistors must be
disabled.
8. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This
PMOS/NMOS contribution to the series resistance is minimal (~10% order).
Table 60. I/O static characteristics (continued)
Symbol Parameter Conditions Min Typ Max Unit
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