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This is information on a product in full production.

March 2019 DS10969 Rev 5 1/204

STM32L475xx

Ultra-low-power Arm

Cortex

-M4 32-bit MCU+FPU, 100DMIPS,

up to 1MB Flash, 128 KB SRAM, USB OTG FS, analog, audio

Datasheet - production data

Features

• Ultra-low-power with FlexPowerControl

– 1.71 V to 3.6 V power supply

– -40 °C to 85/105/125 °C temperature range

– 300 nA in V

BAT

mode: supply for RTC and

32x32-bit backup registers

– 30 nA Shutdown mode (5 wakeup pins)

– 120 nA Standby mode (5 wakeup pins)

– 420 nA Standby mode with RTC

– 1.1 µA Stop 2 mode, 1.4 µA with RTC

– 100 µA/MHz run mode

– Batch acquisition mode (BAM)

– 4 µs wakeup from Stop mode

– Brown out reset (BOR)

– Interconnect matrix

• Core: Arm

32-bit Cortex

-M4 CPU with FPU,

Adaptive real-time accelerator (ART

Accelerator™) allowing 0-wait-state execution

from Flash memory, frequency up to 80 MHz,

MPU, 100DMIPS and DSP instructions

• Performance benchmark

– 1.25 DMIPS/MHz (Drystone 2.1)

– 273.55 CoreMark

(3.42 CoreMark/MHz @

80 MHz)

• Energy benchmark

– 294 ULPMark™ CP score

– 106 ULPMark™ PP score

• Clock Sources

– 4 to 48 MHz crystal oscillator

– 32 kHz crystal oscillator for RTC (LSE)

– Internal 16 MHz factory-trimmed RC (±1%)

– Internal low-power 32 kHz RC (±5%)

– Internal multispeed 100 kHz to 48 MHz

oscillator, auto-trimmed by LSE (better than

±0.25 % accuracy)

– 3 PLLs for system clock, USB, audio, ADC

• Up to 114 fast I/Os, most 5 V-tolerant

• RTC with HW calendar, alarms and calibration

• Up to 21 capacitive sensing channels: support

touchkey, linear and rotary touch sensors

• 16x timers: 2x 16-bit advanced motor-control,

2x 32-bit and 5x 16-bit general purpose, 2x 16-

bit basic, 2x low-power 16-bit timers (available

in Stop mode), 2x watchdogs, SysTick timer

• Memories

– Up to 1 MB Flash, 2 banks read-while-

write, proprietary code readout protection

– Up to 128 KB of SRAM including 32 KB

with hardware parity check

– External memory interface for static

memories supporting SRAM, PSRAM and

NOR memories

– Quad SPI memory interface

• 4x digital filters for sigma delta modulator

• Rich analog peripherals (independent supply)

– 3x 12-bit ADC 5 Msps, up to 16-bit with

hardware oversampling, 200 µA/Msps

– 2x 12-bit DAC output channels, low-power

sample and hold

– 2x operational amplifiers with built-in PGA

– 2x ultra-low-power comparators

• 20x communication interfaces

– USB OTG 2.0 full-speed, LPM and BCD

– 2x SAIs (serial audio interface)

–3x I2C FM+(1 Mbit/s), SMBus/PMBus

– 5x USARTs (ISO 7816, LIN, IrDA, modem)

– 1x LPUART (Stop 2 wake-up)

– 3x SPIs (and 1x Quad SPI)

– CAN (2.0B Active) and SDMMC interface

– SWPMI single wire protocol master I/F

– IRTIM (Infrared interface)

LQFP100 (14 x 14)

LQFP64 (10 x 10)

www.st.com

Downloaded from Arrow.com.

Summary of content (204 pages)

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STM32L475xx Ultra-low-power Arm® Cortex®-M4 32-bit MCU+FPU, 100DMIPS, up to 1MB Flash, 128 KB SRAM, USB OTG FS, analog, audio Datasheet - production data Features • Ultra-low-power with FlexPowerControl – 1.71 V to 3.6 V power supply – -40 °C to 85/105/125 °C temperature range – 300 nA in VBAT mode: supply for RTC and 32x32-bit backup registers – 30 nA Shutdown mode (5 wakeup pins) – 120 nA Standby mode (5 wakeup pins) – 420 nA Standby mode with RTC – 1.1 µA Stop 2 mode, 1.
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STM32L475xx • 14-channel DMA controller • True random number generator • Development support: serial wire debug (SWD), JTAG, Embedded Trace Macrocell™ • All packages are ECOPACK2® compliant • CRC calculation unit, 96-bit unique ID Table 1. Device summary Reference STM32L475xx 2/204 Downloaded from Arrow.com.
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STM32L475xx Contents Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.1 Arm® Cortex®-M4 core with FPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.
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Contents STM32L475xx 3.17 Voltage reference buffer (VREFBUF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.18 Comparators (COMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3.19 Operational amplifier (OPAMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3.20 Touch sensing controller (TSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3.21 Digital filter for Sigma-Delta Modulators (DFSDM) . . . . . . . .
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STM32L475xx 6 Contents Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 6.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 6.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 6.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 6.1.3 Typical curves . . . . . . . . . . . . . . . . . . . .
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Contents 7 STM32L475xx 6.3.26 Timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 6.3.27 Communication interfaces characteristics . . . . . . . . . . . . . . . . . . . . . . 169 6.3.28 FSMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 6.3.29 SWPMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 Package information . . . . . . . . . . . . . . . . . . . .
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STM32L475xx List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Device summary . . . . . . . . . . . . . . . . . . . . .
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List of tables Table 43. Table 44. Table 45. Table 46. Table 47. Table 48. Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. Table 62. Table 63. Table 64. Table 65. Table 66. Table 67. Table 68. Table 69. Table 70. Table 71. Table 72. Table 73. Table 74. Table 75. Table 76. Table 77. Table 78. Table 79. Table 80. Table 81. Table 82. Table 83. Table 84. Table 85. Table 86. Table 87. Table 88. Table 89. Table 90. Table 91.
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STM32L475xx Table 95. Table 96. Table 97. Table 98. Table 99. Table 100. Table 101. Table 102. Table 103. Table 104. Table 105. List of tables Asynchronous multiplexed PSRAM/NOR read-NWAIT timings . . . . . . . . . . . . . . . . . . . . 184 Asynchronous multiplexed PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . . . . . . . . . 186 Asynchronous multiplexed PSRAM/NOR write-NWAIT timings . . . . . . . . . . . . . . . . . . . . 186 Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . .
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List of figures STM32L475xx List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42. Figure 43.
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STM32L475xx 1 Introduction Introduction This datasheet provides the ordering information and mechanical device characteristics of the STM32L475xx microcontrollers. This document should be read in conjunction with the STM32L4x5 reference manual (RM0351). The reference manual is available from the STMicroelectronics website www.st.com. For information on the Arm®(a) Cortex®-M4 core, please refer to the Cortex®-M4 Technical Reference Manual, available from the www.arm.com website. a.
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Description 2 STM32L475xx Description The STM32L475xx devices are the ultra-low-power microcontrollers based on the highperformance Arm® Cortex®-M4 32-bit RISC core operating at a frequency of up to 80 MHz. The Cortex-M4 core features a Floating point unit (FPU) single precision which supports all Arm® single-precision data-processing instructions and data types. It also implements a full set of DSP instructions and a memory protection unit (MPU) which enhances application security.
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STM32L475xx Description Table 2. STM32L475xx family device features and peripheral counts Peripheral Flash memory STM32L475Vx 256KB 512KB SRAM 256KB Yes(1) Quad SPI Comm.
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Description STM32L475xx Table 2. STM32L475xx family device features and peripheral counts (continued) Peripheral STM32L475Vx STM32L475Rx Yes No Internal voltage reference buffer Analog comparator 2 Operational amplifiers 2 Max. CPU frequency 80 MHz Operating voltage Operating temperature Packages 1.71 to 3.6 V Ambient operating temperature: -40 to 85 °C / -40 to 105 °C / -40 to 125 °C Junction temperature: -40 to 105 °C / -40 to 125 °C / -40 to 130 °C LQFP100 LQFP64 1.
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STM32L475xx Description Figure 1.
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Functional overview STM32L475xx 3 Functional overview 3.1 Arm® Cortex®-M4 core with FPU The Arm® Cortex®-M4 with FPU processor is the latest generation of Arm® processors for embedded systems. It was developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced response to interrupts.
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STM32L475xx 3.4 Functional overview Embedded Flash memory STM32L475xx devices feature up to 1 Mbyte of embedded Flash memory available for storing programs and data. The Flash memory is divided into two banks allowing readwhile-write operations. This feature allows to perform a read operation from one bank while an erase or program operation is performed to the other bank. The dual bank boot is also supported. Each bank contains 256 pages of 2 Kbyte.
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Functional overview STM32L475xx The whole non-volatile memory embeds the error correction code (ECC) feature supporting: 3.5 • single error detection and correction • double error detection. • The address of the ECC fail can be read in the ECC register Embedded SRAM STM32L475xx devices feature up to 128 Kbyte of embedded SRAM. This SRAM is split into two blocks: • 96 Kbyte mapped at address 0x2000 0000 (SRAM1) • 32 Kbyte located at address 0x1000 0000 with hardware parity check (SRAM2).
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STM32L475xx 3.7 Functional overview Boot modes At startup, BOOT0 pin and BOOT1 option bit are used to select one of three boot options: • Boot from user Flash • Boot from system memory • Boot from embedded SRAM The boot loader is located in system memory. It is used to reprogram the Flash memory by using USART, I2C, SPI, CAN or USB OTG FS in Device mode through DFU (device firmware upgrade). 3.
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Functional overview STM32L475xx Figure 2. Power supply overview VDDA domain VDDA VSSA 1 x A/D converters 2 x comparators 2 x D/A converters 1 x operational amplifier Voltage reference buffer VDDUSB VSS USB transceivers VDD domain VDDIO1 I/O ring VCORE domain Reset block Temp.
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STM32L475xx Functional overview Figure 3. Power-up/down sequence V 3.6 VDDX(1) VDD VBOR0 1 0.3 Power-on Invalid supply area Operating mode VDDX < VDD + 300 mV Power-down VDDX independent from VDD time MSv47490V1 1. VDDX refers to any power supply among VDDA, VDDUSB. 3.9.2 Power supply supervisor The device has an integrated ultra-low-power brown-out reset (BOR) active in all modes except Shutdown and ensuring proper operation after power-on and during power down.
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Functional overview 3.9.3 STM32L475xx Voltage regulator Two embedded linear voltage regulators supply most of the digital circuitries: the main regulator (MR) and the low-power regulator (LPR). • The MR is used in the Run and Sleep modes and in the Stop 0 mode. • The LPR is used in Low-Power Run, Low-Power Sleep, Stop 1 and Stop 2 modes. It is also used to supply the 32 Kbyte SRAM2 in Standby with SRAM2 retention.
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Downloaded from Arrow.com. Stop 0 LPSleep Sleep LPRun Run Mode DS10969 Rev 5 Range 2 Range 1 LPR Range 2 Range 1 LPR Range2 Range 1 (1) Regulator No No No Yes Yes CPU ON ON(5) ON(4) Off ON(5) ON ON(4) ON(4) ON SRAM ON(4) Flash LSE LSI Any except PLL Any Any except PLL Any Clocks BOR, PVD, PVM RTC, IWDG COMPx (x=1,2) DAC1 OPAMPx (x=1,2) USARTx (x=1...5)(6) LPUART1(6) I2Cx (x=1...3)(7) LPTIMx (x=1,2) *** All other peripherals are frozen.
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/204 Downloaded from Arrow.com. LPR LPR Stop 1 Stop 2 (1) Regulator Mode No No CPU Off Off Flash ON ON SRAM LSE LSI LSE LSI Reset pin, all I/Os BOR, PVD, PVM RTC, IWDG COMPx (x=1..2) I2C3(7) LPUART1(6) LPTIM1 Reset pin, all I/Os BOR, PVD, PVM RTC, IWDG COMPx (x=1..2) USARTx (x=1...5)(6) LPUART1(6) I2Cx (x=1...3)(7) LPTIMx (x=1,2) OTG_FS(8) SWPMI1(9) BOR, PVD, PVM RTC, IWDG COMPx (x=1,2) DAC1 OPAMPx (x=1,2) USARTx (x=1...5)(6) LPUART1(6) I2Cx (x=1...
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Downloaded from Arrow.com. OFF OFF LPR (1) Regulator Powered Off Powered Off CPU Off Off Flash Powered Off Powered Off SRAM2 ON SRAM LSE LSE LSI Clocks Wakeup source Reset pin 5 I/Os (WKUPx)(10) BOR, RTC, IWDG Reset pin 5 I/Os (WKUPx)(10) RTC DMA & Peripherals(2) BOR, RTC, IWDG *** All other peripherals are powered off. *** I/O configuration can be floating, pull-up or pull-down RTC *** All other peripherals are powered off.
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Functional overview STM32L475xx By default, the microcontroller is in Run mode after a system or a power Reset. It is up to the user to select one of the low-power modes described below: • Sleep mode In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can wake up the CPU when an interrupt/event occurs. • Low-power run mode This mode is achieved with VCORE supplied by the low-power regulator to minimize the regulator's operating current.
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STM32L475xx • Functional overview Shutdown mode The Shutdown mode allows to achieve the lowest power consumption. The internal regulator is switched off so that the VCORE domain is powered off. The PLL, the HSI16, the MSI, the LSI and the HSE oscillators are also switched off. The RTC can remain active (Shutdown mode with RTC, Shutdown mode without RTC). The BOR is not available in Shutdown mode. No power voltage monitoring is possible in this mode, therefore the switch to Backup domain is not supported.
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Functional overview STM32L475xx Table 5.
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STM32L475xx Functional overview Table 5.
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Functional overview STM32L475xx Table 5. Functionalities depending on the working mode(1) (continued) - - CRC calculation unit O O O O - - - - - - - - - GPIOs O O O O O O O O (9) 5 pins (11) 5 pins - Peripheral Run Sleep Lowpower run Lowpower sleep - (10) Wakeup capability - Wakeup capability Standby Shutdown Wakeup capability Stop 2 Wakeup capability Stop 0/1 VBAT (10) 1. Legend: Y = Yes (Enable). O = Optional (Disable by default.
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STM32L475xx 3.10 Functional overview Interconnect matrix Several peripherals have direct connections between them. This allows autonomous communication between peripherals, saving CPU resources thus power supply consumption. In addition, these hardware connections allow fast and predictable latency. Depending on peripherals, these interconnections can operate in Run, Sleep, low-power run and sleep, Stop 0, Stop 1 and Stop 2 modes.
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Functional overview STM32L475xx Low-power run Low-power sleep Stop 0 / Stop 1 Stop 2 GPIO Sleep Interconnect source Run Table 6. STM32L475xx peripherals interconnect matrix (continued) TIMx External trigger Y Y Y Y - - LPTIMERx External trigger Y Y Y Y Y (1) ADCx DAC1 DFSDM1 Conversion external trigger Y Y Y Y - - Interconnect destination Interconnect action 1. LPTIM1 only. 32/204 Downloaded from Arrow.com.
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STM32L475xx 3.11 Functional overview Clocks and startup The clock controller (see Figure 4) distributes the clocks coming from different oscillators to the core and the peripherals. It also manages clock gating for low-power modes and ensures clock robustness.
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Functional overview STM32L475xx interrupt is generated if enabled. LSE failure can also be detected and generated an interrupt. • Clock-out capability: – MCO: microcontroller clock output: it outputs one of the internal clocks for external use by the application. Low frequency clocks (LSI, LSE) are available down to Stop 1 low power state. – LSCO: low speed clock output: it outputs LSI or LSE in all low-power modes down to Standby mode. LSE can also be output on LSCO in Shutdown mode.
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STM32L475xx Functional overview Figure 4. Clock tree to IWDG LSI RC 32 kHz LSCO to RTC OSC32_OUT LSE OSC 32.768 kHz /32 OSC32_IN LSE LSI HSE MCO / 1→16 to PWR SYSCLK HSI16 OSC_OUT HSE OSC 4-48 MHz OSC_IN to AHB bus, core, memory and DMA Clock source control MSI PLLCLK AHB PRESC / 1,2,..
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Functional overview 3.12 STM32L475xx General-purpose inputs/outputs (GPIOs) Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog alternate functions. Fast I/O toggling can be achieved thanks to their mapping on the AHB2 bus.
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STM32L475xx Functional overview 3.14 Interrupts and events 3.14.1 Nested vectored interrupt controller (NVIC) The devices embed a nested vectored interrupt controller able to manage 16 priority levels, and handle up to 80 maskable interrupt channels plus the 16 interrupt lines of the Cortex®M4.
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Functional overview 3.15 STM32L475xx Analog to digital converter (ADC) The device embeds 3 successive approximation analog-to-digital converters with the following features: • 12-bit native resolution, with built-in calibration • 5.33 Msps maximum conversion rate with full resolution Down to 18.75 ns sampling time – Increased conversion rate for lower resolution (up to 8.88 Msps for 6-bit resolution) • Up to 16 external channels, some of them shared between ADC1 and ADC2, or ADC1, ADC2 and ADC3.
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STM32L475xx Functional overview To improve the accuracy of the temperature sensor measurement, each device is individually factory-calibrated by ST. The temperature sensor factory calibration data are stored by ST in the system memory area, accessible in read-only mode. Table 8. Temperature sensor calibration values 3.15.2 Calibration value name Description Memory address TS_CAL1 TS ADC raw data acquired at a temperature of 30 °C (± 5 °C), VDDA = VREF+ = 3.
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Functional overview STM32L475xx This digital interface supports the following features: • Up to two DAC output channels • 8-bit or 12-bit output mode • Buffer offset calibration (factory and user trimming) • Left or right data alignment in 12-bit mode • Synchronized update capability • Noise-wave generation • Triangular-wave generation • Dual DAC channel independent or simultaneous conversions • DMA capability for each channel • External triggers for conversion • Sample and hold low-p
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STM32L475xx 3.18 Functional overview Comparators (COMP) The STM32L475xx devices embed two rail-to-rail comparators with programmable reference voltage (internal or external), hysteresis and speed (low speed for low-power) and with selectable output polarity. The reference voltage can be one of the following: • External I/O • DAC output channels • Internal reference voltage or submultiple (1/4, 1/2, 3/4).
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Functional overview STM32L475xx The main features of the touch sensing controller are the following: • Proven and robust surface charge transfer acquisition principle • Supports up to 21 capacitive sensing channels • Up to 3 capacitive sensing channels can be acquired in parallel offering a very good response time • Spread spectrum feature to improve system robustness in noisy environments • Full hardware management of the charge transfer acquisition sequence • Programmable charge transfer freq
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STM32L475xx Functional overview hardware. DFSDM features optional parallel data stream inputs from microcontrollers memory (through DMA/CPU transfers into DFSDM). DFSDM transceivers support several serial interface formats (to support various Σ∆ modulators). DFSDM digital filter modules perform digital processing according user selected filter parameters with up to 24-bit final ADC resolution.
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Functional overview STM32L475xx without having any impact on the timing of “injected” conversions – “injected” conversions for precise timing and with high conversion priority Table 10. DFSDM1 implementation DFSDM features DFSDM1 Number of channels 8 Number of filters 4 Input from internal ADC - Supported trigger sources 3.
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STM32L475xx Functional overview Table 11. Timer feature comparison (continued) Timer type Timer Counter resolution Counter type Prescaler factor DMA request generation Capture/ compare channels Complementary outputs Generalpurpose TIM16, TIM17 16-bit Up Any integer between 1 and 65536 Yes 1 1 Basic TIM6, TIM7 16-bit Up Any integer between 1 and 65536 Yes 0 No 3.23.
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Functional overview 3.23.2 STM32L475xx General-purpose timers (TIM2, TIM3, TIM4, TIM5, TIM15, TIM16, TIM17) There are up to seven synchronizable general-purpose timers embedded in the STM32L475xx (see Table 11 for differences). Each general-purpose timer can be used to generate PWM outputs, or act as a simple time base.
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STM32L475xx Functional overview This low-power timer supports the following features: 3.23.5 • 16-bit up counter with 16-bit autoreload register • 16-bit compare register • Configurable output: pulse, PWM • Continuous/ one shot mode • Selectable software/hardware input trigger • Selectable clock source – Internal clock sources: LSE, LSI, HSI16 or APB clock – External clock source over LPTIM input (working even with no internal clock source running, used by pulse counter application).
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Functional overview 3.24 STM32L475xx Real-time clock (RTC) and backup registers The RTC is an independent BCD timer/counter. It supports the following features: • Calendar with subsecond, seconds, minutes, hours (12 or 24 format), week day, date, month, year, in BCD (binary-coded decimal) format. • Automatic correction for 28, 29 (leap year), 30, and 31 days of the month. • Two programmable alarms. • On-the-fly correction from 1 to 32767 RTC clock pulses.
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STM32L475xx 3.25 Functional overview Inter-integrated circuit interface (I2C) The device embeds three I2C. Refer to Table 12: I2C implementation for the features implementation. The I2C bus interface handles communications between the microcontroller and the serial I2C bus. It controls all I2C bus-specific sequencing, protocol, arbitration and timing. The I2C peripheral supports: • • I2C-bus specification and user manual rev.
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Functional overview 3.26 STM32L475xx Universal synchronous/asynchronous receiver transmitter (USART) The STM32L475xx devices have three embedded universal synchronous receiver transmitters (USART1, USART2 and USART3) and two universal asynchronous receiver transmitters (UART4, UART5). These interfaces provide asynchronous communication, IrDA SIR ENDEC support, multiprocessor communication mode, single-wire half-duplex communication mode and have LIN Master/Slave capability.
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STM32L475xx 3.27 Functional overview Low-power universal asynchronous receiver transmitter (LPUART) The device embeds one Low-Power UART. The LPUART supports asynchronous serial communication with minimum power consumption. It supports half duplex single wire communication and modem operations (CTS/RTS). It allows multiprocessor communication. The LPUART has a clock domain independent from the CPU clock, and can wakeup the system from Stop mode using baudrates up to 220 Kbaud.
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Functional overview 3.28 STM32L475xx Serial peripheral interface (SPI) Three SPI interfaces allow communication up to 40 Mbits/s in master and up to 24 Mbits/s slave modes, in half-duplex, full-duplex and simplex modes. The 3-bit prescaler gives 8 master mode frequencies and the frame size is configurable from 4 bits to 16 bits. The SPI interfaces support NSS pulse mode, TI mode and Hardware CRC calculation. All SPI interfaces can be served by the DMA controller. 3.
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STM32L475xx Functional overview Table 14. SAI implementation SAI features(1) SAI1 SAI2 I2S, LSB or MSB-justified, PCM/DSP, TDM, AC’97 X X Mute mode X X Stereo/Mono audio frame capability. X X 16 slots X X Data size configurable: 8-, 10-, 16-, 20-, 24-, 32-bit X X X (8 Word) X (8 Word) X X FIFO Size SPDIF 1. X: supported 3.
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Functional overview STM32L475xx The CAN peripheral supports: • Supports CAN protocol version 2.0 A, B Active • Bit rates up to 1 Mbit/s • Transmission • • • 3.
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STM32L475xx Functional overview The major features are: • Combined Rx and Tx FIFO size of 1.25 KB with dynamic FIFO sizing • Supports the session request protocol (SRP) and host negotiation protocol (HNP) • 1 bidirectional control endpoint + 5 IN endpoints + 5 OUT endpoints • 12 host channels with periodic OUT support • HNP/SNP/IP inside (no need for any external resistor) • USB 2.0 LPM (Link Power Management) support • Battery Charging Specification Revision 1.
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Functional overview STM32L475xx The Quad SPI interface supports: • Three functional modes: indirect, status-polling, and memory-mapped • SDR and DDR support • Fully programmable opcode for both indirect and memory mapped mode • Fully programmable frame format for both indirect and memory mapped mode • Each of the 5 following phases can be configured independently (enable, length, single/dual/quad communication) – 56/204 Downloaded from Arrow.com.
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STM32L475xx Functional overview 3.36 Development support 3.36.1 Serial wire JTAG debug port (SWJ-DP) The Arm® SWJ-DP interface is embedded, and is a combined JTAG and serial wire debug port that enables either a serial wire debug or a JTAG probe to be connected to the target.
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Pinouts and pin description 4 STM32L475xx Pinouts and pin description 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 VDD VSS PE1 PE0 PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PC12 PC11 PC10 PA15 PA14 Figure 6.
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STM32L475xx Pinouts and pin description VDD VSS PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 (NJTRST) PB3 (JTDO-TRACESWO) PD2 PC12 PC11 PC10 PA15 (JTDI) PA14 (JTCK-SWCLK) 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 Figure 7.
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Pinouts and pin description STM32L475xx Table 15. Legend/abbreviations used in the pinout table (continued) Name Abbreviation Definition Alternate Functions selected through GPIOx_AFR registers functions Pin functions Additional Functions directly selected/enabled through peripheral registers functions 1. The related I/O structures in Table 16 are: FT_f, FT_fa, FT_f, FT_fa. 2. The related I/O structures in Table 16 are: FT_u. 3. The related I/O structures in Table 16 are: FT_a, FT_fa, TT_a. Table 16.
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STM32L475xx Pinouts and pin description Table 16.
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Pinouts and pin description STM32L475xx Table 16.
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STM32L475xx Pinouts and pin description Table 16.
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Pinouts and pin description STM32L475xx Table 16.
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STM32L475xx Pinouts and pin description Table 16.
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Pinouts and pin description STM32L475xx Table 16.
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STM32L475xx Pinouts and pin description Table 16.
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Pinouts and pin description STM32L475xx Table 16.
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/204 Downloaded from Arrow.com. - - PH0 PH1 SYS_AF - - - TIM1/TIM2/ TIM3/TIM4/ TIM5 TIM1/TIM2/ TIM5/TIM8/ LPTIM1 - AF2 AF1 1. Please refer to Table 18 for AF8 to AF15. Port H Port AF0 - - TIM8 AF3 - - I2C1/I2C2/I2C3 AF4 AF5 - - SPI1/SPI2 Table 17.
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Downloaded from Arrow.com. DS10969 Rev 5 - - - - - - - - - - - - - - - - - PE1 PE2 PE3 PE4 PE5 PE6 PE7 PE8 PE9 PE10 PE11 PE12 PE13 PE14 PE15 PH0 PH1 - - - - - - TSC_G5_IO4 TSC_G5_IO3 TSC_G5_IO2 TSC_G5_IO1 - - - - TSC_G7_IO4 TSC_G7_IO3 TSC_G7_IO2 TSC_G7_IO1 1. Please refer to Table 17 for AF0 to AF7.
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Memory mapping 5 STM32L475xx Memory mapping Figure 8.
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STM32L475xx Memory mapping Table 19.
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Memory mapping STM32L475xx Table 19.
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STM32L475xx Memory mapping Table 19.
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Memory mapping STM32L475xx Table 19. STM32L475xx memory map and peripheral register boundary addresses(1) (continued) Bus APB1 Boundary address Downloaded from Arrow.com.
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STM32L475xx Electrical characteristics 6 Electrical characteristics 6.1 Parameter conditions Unless otherwise specified, all voltages are referenced to VSS. 6.1.1 Minimum and maximum values Unless otherwise specified, the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at TA = 25 °C and TA = TAmax (given by the selected temperature range).
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Electrical characteristics 6.1.6 STM32L475xx Power supply scheme Figure 11. Power supply scheme VBAT Backup circuitry (LSE, RTC, Backup registers) 1.55 – 3.6 V Power switch VDD VCORE n x VDD Regulator OUT n x 100 nF GPIOs IN +1 x 4.7 μF Level shifter VDDIO1 IO logic Kernel logic (CPU, Digital & Memories) n x VSS VDDA VDDA VREF 10 nF +1 μF 100 nF +1 μF VREF+ VREF- ADCs/ DACs/ OPAMPs/ COMPs/ VREFBUF VSSA MSv40913V1 Caution: 86/204 Downloaded from Arrow.com.
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STM32L475xx 6.1.7 Electrical characteristics Current consumption measurement Figure 12. Current consumption measurement scheme IDD_USB VDDUSB IDD_VBAT VBAT IDD VDD IDDA VDDA MSv40912V1 6.2 Absolute maximum ratings Stresses above the absolute maximum ratings listed in Table 20: Voltage characteristics, Table 21: Current characteristics and Table 22: Thermal characteristics may cause permanent damage to the device.
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Electrical characteristics STM32L475xx Table 20. Voltage characteristics(1) (continued) Symbol |∆VDDx| |VSSx-VSS| Ratings Min Max Unit Variations between different VDDX power pins of the same domain - 50 mV Variations between all the different ground pins(5) - 50 mV 1. All main power (VDD, VDDA, VDDUSB, VBAT) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the permitted range. 2. VIN maximum must always be respected.
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STM32L475xx Electrical characteristics Table 22. Thermal characteristics Symbol TSTG TJ Ratings Storage temperature range Maximum junction temperature DS10969 Rev 5 Value Unit –65 to +150 °C 150 °C 89/204 190 Downloaded from Arrow.com.
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Electrical characteristics STM32L475xx 6.3 Operating conditions 6.3.1 General operating conditions Table 23. General operating conditions Symbol Parameter Conditions Min Max fHCLK Internal AHB clock frequency - 0 80 fPCLK1 Internal APB1 clock frequency - 0 80 fPCLK2 Internal APB2 clock frequency - 0 80 Standard operating voltage - VDD VDDA Analog supply voltage 1.71 VBAT VDDUSB USB supply voltage TJ 1.55 3.6 V 3.0 3.6 0 3.6 -0.3 VDDIOx+0.3 0 9 -0.
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STM32L475xx Electrical characteristics 4. If TA is lower, higher PD values are allowed as long as TJ does not exceed TJmax (see Section 7.3: Thermal characteristics). 5. In low-power dissipation state, TA can be extended to this range as long as TJ does not exceed TJmax (see Section 7.3: Thermal characteristics). 6.3.2 Operating conditions at power-up / power-down The parameters given in Table 24 are derived from tests performed under the ambient temperature condition summarized in Table 23. Table 24.
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Electrical characteristics STM32L475xx Table 25. Embedded reset and power control block characteristics (continued) Conditions(1) Min Typ Max Rising edge 2.26 2.31 2.36 Falling edge 2.15 2.20 2.25 Rising edge 2.41 2.46 2.51 Falling edge 2.31 2.36 2.41 Rising edge 2.56 2.61 2.66 Falling edge 2.47 2.52 2.57 Rising edge 2.69 2.74 2.79 Falling edge 2.59 2.64 2.69 Rising edge 2.85 2.91 2.96 Falling edge 2.75 2.81 2.86 Rising edge 2.92 2.98 3.04 Falling edge 2.
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STM32L475xx 6.3.4 Electrical characteristics Embedded voltage reference The parameters given in Table 26 are derived from tests performed under the ambient temperature and supply voltage conditions summarized in Table 23: General operating conditions. Table 26. Embedded internal voltage reference Symbol VREFINT Parameter Internal reference voltage Conditions –40 °C < TA < +130 °C Min Typ Max Unit 1.182 1.212 1.
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Electrical characteristics STM32L475xx Figure 13. VREFINT versus temperature V 1.235 1.23 1.225 1.22 1.215 1.21 1.205 1.2 1.195 1.19 1.185 -40 -20 0 20 40 Mean 60 Min 80 100 120 °C Max MSv40169V1 94/204 Downloaded from Arrow.com.
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STM32L475xx 6.3.5 Electrical characteristics Supply current characteristics The current consumption is a function of several parameters and factors such as the operating voltage, ambient temperature, I/O pin loading, device software configuration, operating frequencies, I/O pin switching rate, program location in memory and executed binary code. The current consumption is measured as described in Figure 12: Current consumption measurement scheme.
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/204 Downloaded from Arrow.com. Supply current in fHCLK = fMSI Low-power all peripherals disable run mode IDD_ALL (Run) IDD_ALL (LPRun) DS10969 Rev 5 8.25 6.28 4.24 3.21 2.19 272 154 78 42 64 MHz Range 1 48 MHz 32 MHz 24 MHz 16 MHz 2 MHz 1 MHz 400 kHz 100 kHz 1. Guaranteed by characterization results, unless otherwise specified. 9.24 72 MHz 0.14 100 kHz 10.2 0.23 1 MHz 0.34 2 MHz 0.98 8 MHz 0.55 1.83 16 MHz 4 MHz 2.88 26 MHz 73 108 184 303 2.24 3.27 4.30 6.35 8.32 9.31 10.
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Downloaded from Arrow.com. Supply current in fHCLK = fMSI Low-power all peripherals disable run IDD_ALL (Run) IDD_ALL (LPRun) DS10969 Rev 5 4.16 2.93 358 197 97 47 24 MHz 16 MHz 2 MHz 1 MHz 400 kHz 100 kHz 1. Guaranteed by characterization results, unless otherwise specified. 7.64 5.49 32 MHz 9.06 10.0 80 MHz 8.96 0.14 100 kHz 64 MHz 0.27 1 MHz 72 MHz 0.42 2 MHz 1.26 8 MHz 0.71 2.24 16 MHz 4 MHz 3.15 26 MHz 77 126 230 392 2.99 4.22 5.57 7.72 9.04 9.13 10.1 0.17 0.30 0.
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/204 Downloaded from Arrow.com. fHCLK = fMSI all peripherals disable FLASH in power-down Supply current in low-power run mode DS10969 Rev 5 Range 1 61 26 100 kHz 242 2 MHz 400 kHz 2.18 16 MHz 130 3.20 1 MHz 4.22 24 MHz 8.25 64 MHz 32 MHz 9.25 72 MHz 6.26 10.2 80 MHz 48 MHz 0.22 0.12 1 MHz 100 kHz 0.33 2 MHz 0.97 0.54 8 MHz 4 MHz 2.88 1.83 26 MHz 16 MHz 25 °C fHCLK 1. Guaranteed by characterization results, unless otherwise specified.
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STM32L475xx Electrical characteristics Table 30. Typical current consumption in Run and Low-power run modes, with different codes running from Flash, ART enable (Cache ON Prefetch OFF) Conditions - IDD_ALL (Run) Supply current in Run mode fHCLK = fHSE up to 48 MHz included, bypass mode PLL ON above 48 MHz all peripherals disable Code 25 °C Reduced code(1) 2.9 111 Coremark 3.1 118 Dhrystone 2.1 3.1 Fibonacci 2.9 112 2.8 108 Reduced code 10.2 127 Coremark 10.9 136 Dhrystone 2.1 11.
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Electrical characteristics STM32L475xx Table 31. Typical current consumption in Run and Low-power run modes, with different codes running from Flash, ART disable (continued) Conditions Symbol Parameter - TYP Unit Voltage scaling Code Reduced code(1) IDD_ALL (LPRun) Supply current in fHCLK = fMSI = 2 MHz Low-power all peripherals disable run TYP Unit 25 °C 25 °C 358 179 Coremark 392 Dhrystone 2.1 390 196 Fibonacci 385 192 While(1) 385 192 µA 195 µA/MHz 1.
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Downloaded from Arrow.com. DS10969 Rev 5 IDD_ALL (Sleep) 0.18 0.15 0.12 2.96 2.69 2.41 1.88 1.30 1.01 0.71 96 65 43 33 1 MHz 100 kHz 80 MHz 72 MHz 64 MHz Range 1 48 MHz 32 MHz 24 MHz 16 MHz 2 MHz 1 MHz 400 kHz 100 kHz 8 MHz 2 MHz 0.61 0.36 16 MHz 0.24 0.92 26 MHz 63 73 94 126 0.75 1.05 1.35 1.93 2.45 2.73 3.00 0.14 0.17 0.20 0.27 0.40 0.65 0.96 25 °C 55 °C fHCLK 4 MHz Range 2 Voltage scaling 1. Guaranteed by characterization results, unless otherwise specified.
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Downloaded from Arrow.com. Parameter 3V 3V 3V Wakeup clock is MSI = 4 MHz, voltage Range 2. See (4). Wakeup clock is HSI16 = 16 MHz, voltage Range 1. See (4). VDD Wakeup clock is MSI = 48 MHz, voltage Range 1. See (4). - Conditions 2.1 2.24 1.9 - - - 25 °C 55 °C - - - 85 °C TYP - - - - - - 105 °C 125 °C 25 °C 55 °C DS10969 Rev 5 Parameter Supply current in Stop 1 mode, RTC disabled Symbol IDD_ALL (Stop 1) - - Conditions 6.70 3.6 V 25.1 24.9 93.8 93.
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/204 Downloaded from Arrow.com. Parameter RTC clocked by LSI - Conditions DS10969 Rev 5 6.85 3.6 V 1.8 V 1.62 3V 25.2 - - - 25.4 25.2 25.1 25.0 26.0 25.7 25.3 25.2 25.7 25.4 - - - 94.1 93.6 93.2 93.0 96.1 95.0 94.2 93.4 95.2 94.2 93.7 - - - 212.3 210.3 209.3 208.
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Downloaded from Arrow.com. Supply current in Stop 0 mode, RTC disabled IDD_ALL (Stop 0) 108 110 111 113 1.8 V 2.4 V 3V 3.6 V 2. Guaranteed by test in production. 137 135 134 132 25 °C 55 °C VDD Conditions 1. Guaranteed by characterization results, unless otherwise specified. Parameter Symbol 222 220 219 217 85 °C TYP 363 360 358 356 642 637 634 631 166 161 158 153 105 °C 125 °C 25 °C Table 37.
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/204 Downloaded from Arrow.com. IDD_ALL (Standby) IDD_ALL (Standby with RTC) Supply current in Standby mode (backup registers retained), RTC disabled Supply current in Standby mode (backup registers retained), RTC enabled Parameter Symbol DS10969 Rev 5 114 138 1.8 V 2.4 V - 198 317 391 3.6 V 1.8 V 2.4 V - 671 853 396 2.4 V 796 961 416 514 652 821 1.8 V 2.4 V RTC clocked by LSE quartz (3) in low drive mode 3 V 3.6 V 1226 640 1111 528 710 3V 527 289 - 1.
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Downloaded from Arrow.com. Supply current to be added in Standby mode when SRAM2 is retained Supply current during wakeup from Standby mode Parameter Wakeup clock is MSI = 4 MHz. See (5). - - Conditions 236 235 3V 3.
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/204 Downloaded from Arrow.com. Supply current in Shutdown mode (backup registers retained) RTC enabled IDD_ALL (Shutdown with RTC) Wakeup clock is MSI = 4 MHz. See (3). RTC clocked by LSE quartz (2) in low drive mode RTC clocked by LSE bypassed at 32768 Hz - Conditions 729 3.
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Downloaded from Arrow.com. RTC disabled - Conditions RTC enabled and clocked by LSE quartz(2) RTC enabled and Backup domain clocked by LSE supply current bypassed at 32768 Hz Parameter 494 630 3V 3.6 V 388 302 1.8 V 2.4 V 508 3.6 V 183 1.8 V 376 10 3.6 V 268 6 3V 3V 5.27 2.4 V 2.
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Electrical characteristics STM32L475xx I/O system current consumption The current consumption of the I/O system has two components: static and dynamic. I/O static current consumption All the I/Os used as inputs with pull-up generate current consumption when the pin is externally held low. The value of this current consumption can be simply computed by using the pull-up/pull-down resistors values given in Table 60: I/O static characteristics.
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STM32L475xx Electrical characteristics On-chip peripheral current consumption The current consumption of the on-chip peripherals is given in Table 41.
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Electrical characteristics STM32L475xx Table 41. Peripheral current consumption (continued) Range 1 Range 2 Low-power run and sleep SRAM2 1.6 1.4 1.6 TSC 1.8 1.4 1.6 118.5 77.3 87.6 AHB to APB1 bridge 0.9 0.7 0.9 CAN1 4.6 4.0 4.4 DAC1 2.4 1.9 2.2 I2C1 independent clock domain 3.7 3.1 3.2 I2C1 APB clock domain 1.3 1.1 1.5 I2C2 independent clock domain 3.7 3.0 3.2 I2C2 APB clock domain 1.4 1.1 1.5 I2C3 independent clock domain 2.9 2.3 2.
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STM32L475xx Electrical characteristics Table 41. Peripheral current consumption (continued) Range 1 Range 2 Low-power run and sleep USART2 independent clock domain 4.1 3.6 3.8 USART2 APB clock domain 1.4 1.1 1.5 USART3 independent clock domain 4.7 4.1 4.2 USART3 APB clock domain 1.5 1.3 1.7 UART4 independent clock domain 3.9 3.2 3.5 UART4 APB clock domain 1.5 1.3 1.6 UART5 independent clock domain 3.9 3.2 3.5 UART5 APB clock domain 1.3 1.2 1.4 WWDG 0.5 0.5 0.
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Electrical characteristics STM32L475xx 1. The BusMatrix is automatically active when at least one master is ON (CPU, DMA). 2. The GPIOx (x= A…H) dynamic current consumption is approximately divided by a factor two versus this table values when the GPIO port is locked thanks to LCKK and LCKy bits in the GPIOx_LCKR register.
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STM32L475xx Electrical characteristics Table 42.
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Electrical characteristics STM32L475xx Table 43. Regulator modes transition times(1) Symbol Parameter tWULPRUN tVOST Conditions Typ Max Wakeup time from Low-power run mode to Code run with MSI 2 MHz Run mode(2) 5 7 Regulator transition time from Range 2 to Range 1 or Range 1 to Range 2(3) 20 40 Typ Max Stop 0 mode - 1.7 Stop 1 mode and Stop 2 mode - 8.5 Unit µs Code run with MSI 24 MHz 1. Guaranteed by characterization results. 2. Time until REGLPF flag is cleared in PWR_SR2. 3.
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STM32L475xx Electrical characteristics Figure 14. High-speed external clock source AC timing diagram tw(HSEH) VHSEH 90% 10% VHSEL tr(HSE) tf(HSE) t tw(HSEL) THSE MS19214V2 Low-speed external user clock generated from an external source In bypass mode the LSE oscillator is switched off and the input pin is a standard GPIO. The external clock signal has to respect the I/O characteristics in Section 6.3.14. However, the recommended clock input waveform is shown in Figure 15. Table 46.
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Electrical characteristics STM32L475xx High-speed external clock generated from a crystal/ceramic resonator The high-speed external (HSE) clock can be supplied with a 4 to 48 MHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on design simulation results obtained with typical external components specified in Table 47.
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STM32L475xx Note: Electrical characteristics For information on selecting the crystal, refer to the application note AN2867 “Oscillator design guide for ST microcontrollers” available from the ST website www.st.com. Figure 16. Typical application with an 8 MHz crystal Resonator with integrated capacitors CL1 OSC_IN 8 MHz resonator CL2 REXT (1) fHSE RF Bias controlled gain OSC_OUT MS19876V1 1. REXT value depends on the crystal characteristics.
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Electrical characteristics STM32L475xx 1. Guaranteed by design. 2. Refer to the note and caution paragraphs below the table, and to the application note AN2867 “Oscillator design guide for ST microcontrollers”. 3. tSU(LSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 kHz oscillation is reached.
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STM32L475xx 6.3.8 Electrical characteristics Internal clock source characteristics The parameters given in Table 49 are derived from tests performed under ambient temperature and supply voltage conditions summarized in Table 23: General operating conditions. The provided curves are characterization results, not tested in production. High-speed internal (HSI16) RC oscillator Table 49.
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Electrical characteristics STM32L475xx Figure 18. HSI16 frequency versus temperature MHz 16.4 +2 % 16.3 +1.5 % 16.2 +1 % 16.1 16 15.9 -1 % 15.8 -1.5 % 15.7 -2 % 15.6 -40 -20 0 Mean 20 40 60 min 80 100 120 °C max MSv39299V2 122/204 Downloaded from Arrow.com.
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STM32L475xx Electrical characteristics Multi-speed internal (MSI) RC oscillator Table 50. MSI oscillator characteristics(1) Symbol Parameter Conditions Min Typ Max Range 0 99 100 101 Range 1 198 200 202 Range 2 396 400 404 Range 3 792 800 808 Range 4 0.99 1 1.01 Range 5 1.98 2 2.02 Range 6 3.96 4 4.04 Range 7 7.92 8 8.08 Range 8 15.8 16 16.16 Range 9 23.8 24 24.4 Range 10 31.7 32 32.32 Range 11 47.5 48 48.48 Range 0 - 98.304 - Range 1 - 196.
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Electrical characteristics STM32L475xx Table 50. MSI oscillator characteristics(1) (continued) Symbol Parameter Conditions Min Typ VDD=1.62 V to 3.6 V -1.2 - VDD=2.4 V to 3.6 V -0.5 - VDD=1.62 V to 3.6 V -2.5 - VDD=2.4 V to 3.6 V -0.8 - VDD=1.62 V to 3.6 V -5 - VDD=2.4 V to 3.6 V -1.
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STM32L475xx Electrical characteristics Table 50. MSI oscillator characteristics(1) (continued) Symbol IDD(MSI)(6) Parameter MSI oscillator power consumption Conditions MSI and PLL mode Min Typ Max Range 0 - - 0.6 1 Range 1 - - 0.8 1.2 Range 2 - - 1.2 1.7 Range 3 - - 1.9 2.5 Range 4 - - 4.7 6 Range 5 - - 6.5 9 Range 6 - - 11 15 Range 7 - - 18.5 25 Range 8 - - 62 80 Range 9 - - 85 110 Range 10 - - 110 130 Range 11 - - 155 190 Unit µA 1.
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Electrical characteristics STM32L475xx Figure 19. Typical current consumption versus MSI frequency Low-speed internal (LSI) RC oscillator Table 51. LSI oscillator characteristics(1) Symbol fLSI tSU(LSI)(2) tSTAB(LSI)(2) IDD(LSI)(2) Parameter LSI Frequency Conditions Min Typ Max VDD = 3.0 V, TA = 30 °C 31.04 - 32.96 VDD = 1.62 to 3.6 V, TA = -40 to 125 °C 29.
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STM32L475xx Electrical characteristics Table 52. PLL, PLLSAI1, PLLSAI2 characteristics(1) Symbol fPLL_IN Parameter Conditions Min Typ Max Unit PLL input clock(2) - 4 - 16 MHz PLL input clock duty cycle - 45 - 55 % Voltage scaling Range 1 2.0645 - 80 Voltage scaling Range 2 2.
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Electrical characteristics STM32L475xx Table 53. Flash memory characteristics(1) (continued) Symbol IDD Parameter Conditions Average consumption from VDD Maximum current (peak) Typ Max Write mode 3.4 - Erase mode 3.4 - Write mode 7 (for 2 μs) - Erase mode 7 (for 41 μs) - Unit mA 1. Guaranteed by design. Table 54.
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STM32L475xx 6.3.11 Electrical characteristics EMC characteristics Susceptibility tests are performed on a sample basis during device characterization. Functional EMS (electromagnetic susceptibility) While a simple application is executed on the device (toggling 2 LEDs through I/O ports). the device is stressed by two electromagnetic events until a failure occurs.
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Electrical characteristics STM32L475xx Prequalification trials Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1 second. To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015).
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STM32L475xx Electrical characteristics Static latch-up Two complementary static tests are required on six parts to assess the latch-up performance: • A supply overvoltage is applied to each power supply pin. • A current injection is applied to each input, output and configurable I/O pin. These tests are compliant with EIA/JESD 78A IC latch-up standard. Table 58. Electrical sensitivities Symbol LU 6.3.
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Electrical characteristics 6.3.14 STM32L475xx I/O port characteristics General input/output characteristics Unless otherwise specified, the parameters given in Table 60 are derived from tests performed under the conditions summarized in Table 23: General operating conditions. All I/Os are designed as CMOS- and TTL-compliant (except BOOT0). Table 60. I/O static characteristics Symbol VIL(1) VIH (1) Parameter Conditions 132/204 Downloaded from Arrow.com.
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STM32L475xx Electrical characteristics Table 60. I/O static characteristics (continued) Symbol Parameter FT_xx input leakage current(3)(5) Ilkg(4) FT_u and PC3 I/O TT_xx input leakage current Conditions Min Typ Max VIN ≤ Max(VDDXXX)(6)(7) - - ±100 Max(VDDXXX) ≤ VIN ≤ Max(VDDXXX)+1 V(6)(7) - - 650 Max(VDDXXX)+1 V < VIN ≤ 5.5 V(6)(7) - - 200 VIN ≤ Max(VDDXXX)(6)(7) - - ±150 Max(VDDXXX) ≤ VIN ≤ Max(VDDXXX)+1 V(6)(7) - - 2500(3) Max(VDDXXX)+1 V < VIN ≤ 5.
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Electrical characteristics STM32L475xx All I/Os are CMOS- and TTL-compliant (no software configuration required). Their characteristics cover more than the strict CMOS-technology or TTL parameters. The coverage of these requirements is shown in Figure 20 for standard I/Os, and in Figure 20 for 5 V tolerant I/Os. Figure 20. I/O input characteristics TTL requirement Vih min = 2V x V DDIO di este n pr odu T Base Bas d u on sim lation simu ed on T cti M on C OS ire requ .
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STM32L475xx Electrical characteristics Output voltage levels Unless otherwise specified, the parameters given in the table below are derived from tests performed under the ambient temperature and supply voltage conditions summarized in Table 23: General operating conditions. All I/Os are CMOS- and TTL-compliant (FT OR TT unless otherwise specified). Table 61. Output voltage characteristics(1) Symbol VOL VOH Parameter Conditions Min Max - 0.4 VDDIOx-0.4 - - 0.4 2.4 - - 1.3 VDDIOx-1.
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Electrical characteristics STM32L475xx Table 62. I/O AC characteristics(1)(2) Speed Symbol Fmax Parameter Maximum frequency 00 Tr/Tf Fmax Output rise and fall time Maximum frequency 01 Tr/Tf 136/204 Downloaded from Arrow.com. Output rise and fall time Conditions Min Max C=50 pF, 2.7 V≤VDDIOx≤3.6 V - 5 C=50 pF, 1.62 V≤VDDIOx≤2.7 V - 1 C=50 pF, 1.08 V≤VDDIOx≤1.62 V - 0.1 C=10 pF, 2.7 V≤VDDIOx≤3.6 V - 10 C=10 pF, 1.62 V≤VDDIOx≤2.7 V - 1.5 C=10 pF, 1.08 V≤VDDIOx≤1.62 V - 0.
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STM32L475xx Electrical characteristics Table 62. I/O AC characteristics(1)(2) (continued) Speed Symbol Fmax Parameter Maximum frequency 10 Tr/Tf Fmax Output rise and fall time Maximum frequency 11 Tr/Tf Fm+ Fmax Tf Output rise and fall time Maximum frequency Output fall time (4) Conditions Min Max C=50 pF, 2.7 V≤VDDIOx≤3.6 V - 50 C=50 pF, 1.62 V≤VDDIOx≤2.7 V - 25 C=50 pF, 1.08 V≤VDDIOx≤1.62 V - 5 C=10 pF, 2.7 V≤VDDIOx≤3.6 V - 100(3) C=10 pF, 1.62 V≤VDDIOx≤2.7 V - 37.
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Electrical characteristics STM32L475xx Figure 21. I/O AC characteristics definition(1) 90% 10% 50% 50% 10% 90% t f(IO)out t r(IO)out T Maximum frequency is achieved if (t r + t f (≤ 2/3)T and if the duty cycle is (45-55%) when loaded by the specified capacitance. MS32132V2 1. Refer to Table 62: I/O AC characteristics. 6.3.15 NRST pin characteristics The NRST pin input driver uses the CMOS technology. It is connected to a permanent pullup resistor, RPU.
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STM32L475xx Electrical characteristics Figure 22. Recommended NRST pin protection External reset circuit(1) VDD RPU NRST(2) Internal reset Filter 0.1 μF MS19878V3 1. The reset network protects the device against parasitic resets. 2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in Table 63: NRST pin characteristics. Otherwise the reset will not be taken into account by the device. 3.
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Electrical characteristics 6.3.18 STM32L475xx Analog-to-Digital converter characteristics Unless otherwise specified, the parameters given in Table 66 are preliminary values derived from tests performed under ambient temperature, fPCLK frequency and VDDA supply voltage conditions summarized in Table 23: General operating conditions. Note: It is recommended to perform a calibration after each power-up. Table 66.
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STM32L475xx Electrical characteristics Table 66. ADC characteristics(1) (2) (continued) Symbol Parameter Conditions Min Typ Max 2.5 3 3.5 - - 3.0 - - 3.25 - - 3.125 0.03125 - 8.00625 µs - 2.5 - 640.5 1/fADC - - - 20 µs 0.1875 - 8.
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Electrical characteristics STM32L475xx Table 67. Maximum ADC RAIN(1)(2) Resolution 12 bits 10 bits 8 bits 6 bits Sampling cycle @80 MHz Sampling time [ns] @80 MHz 2.5 Fast channels(3) Slow channels(4) 31.25 100 N/A 6.5 81.25 330 100 12.5 156.25 680 470 24.5 306.25 1500 1200 47.5 593.75 2200 1800 92.5 1156.25 4700 3900 247.5 3093.75 12000 10000 640.5 8006.75 39000 33000 2.5 31.25 120 N/A 6.5 81.25 390 180 12.5 156.25 820 560 24.5 306.25 1500 1200 47.
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STM32L475xx Electrical characteristics 2. The I/O analog switch voltage booster is enable when VDDA < 2.4 V (BOOSTEN = 1 in the SYSCFG_CFGR1 when VDDA < 2.4V). It is disable when VDDA ≥ 2.4 V. 3. Fast channels are: PC0, PC1, PC2, PC3, PA0. 4. Slow channels are: all ADC inputs except the fast channels. DS10969 Rev 5 143/204 190 Downloaded from Arrow.com.
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Electrical characteristics STM32L475xx Table 68. ADC accuracy - limited test conditions 1(1)(2)(3) Symbol Parameter ET Total unadjusted error EO Conditions(4) Offset error Single ended Differential Single ended Differential Single ended EG Gain error Differential ED EL Differential linearity ADC clock frequency ≤ error 80 MHz, Sampling rate ≤ 5.
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STM32L475xx Electrical characteristics Table 68. ADC accuracy - limited test conditions 1(1)(2)(3) (continued) Symbol THD Conditions(4) Parameter Total harmonic distortion ADC clock frequency ≤ Single 80 MHz, ended Sampling rate ≤ 5.33 Msps, VDDA = VREF+ = 3 V, Differential TA = 25 °C Min Typ Max Unit Fast channel (max speed) - -74 -73 Slow channel (max speed) - -74 -73 Fast channel (max speed) - -79 -76 Slow channel (max speed) - -79 -76 dB 1. Guaranteed by design. 2.
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Electrical characteristics STM32L475xx Table 69. ADC accuracy - limited test conditions 2(1)(2)(3) Symbol Parameter ET Total unadjusted error EO Conditions(4) Offset error Single ended Differential Single ended Differential Single ended EG Gain error Differential ED EL Differential linearity error ADC clock frequency ≤ 80 MHz, Sampling rate ≤ 5.
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STM32L475xx Electrical characteristics Table 69. ADC accuracy - limited test conditions 2(1)(2)(3) (continued) Symbol THD Conditions(4) Parameter Total harmonic distortion Fast channel (max speed) Single ADC clock frequency ≤ ended Slow channel (max speed) 80 MHz, Sampling rate ≤ 5.33 Msps, Fast channel (max speed) Differential 2 V ≤ VDDA Slow channel (max speed) Min Typ Max Unit - -74 -65 - -74 -67 - -79 -70 - -79 -71 dB 1. Guaranteed by design. 2.
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Electrical characteristics STM32L475xx Table 70. ADC accuracy - limited test conditions 3(1)(2)(3) Symbol Parameter ET Total unadjusted error EO Conditions(4) Offset error Single ended Differential Single ended Differential Single ended EG Gain error Differential ED EL Differential linearity ADC clock frequency ≤ error 80 MHz, Sampling rate ≤ 5.33 Msps, 1.65 V ≤ VDDA = VREF+ ≤ 3.
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STM32L475xx Electrical characteristics Table 70. ADC accuracy - limited test conditions 3(1)(2)(3) (continued) Symbol THD Conditions(4) Parameter Total harmonic distortion ADC clock frequency ≤ Single 80 MHz, ended Sampling rate ≤ 5.33 Msps, 1.65 V ≤ VDDA = VREF+ ≤ Differential 3.6 V, Voltage scaling Range 1 Min Typ Max Unit Fast channel (max speed) - -69 -67 Slow channel (max speed) - -71 -67 Fast channel (max speed) - -72 -71 Slow channel (max speed) - -72 -71 dB 1.
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Electrical characteristics STM32L475xx Table 71. ADC accuracy - limited test conditions 4(1)(2)(3) Symbol Parameter ET Total unadjusted error EO Offset error Conditions(4) Single ended Differential Single ended Differential Single ended EG Gain error Differential ED EL Differential linearity ADC clock frequency ≤ error 26 MHz, 1.65 V ≤ VDDA = VREF+ ≤ 3.
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STM32L475xx Electrical characteristics Table 71. ADC accuracy - limited test conditions 4(1)(2)(3) (continued) Symbol THD Conditions(4) Parameter Total harmonic distortion ADC clock frequency ≤ 26 MHz, 1.65 V ≤ VDDA = VREF+ ≤ 3.6 V, Voltage scaling Range 2 Single ended Differential Min Typ Max Unit Fast channel (max speed) - -71 -69 Slow channel (max speed) - -71 -69 Fast channel (max speed) - -73 -72 Slow channel (max speed) - -73 -72 dB 1. Guaranteed by design. 2.
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Electrical characteristics STM32L475xx Figure 23. ADC accuracy characteristics VSSA EG (1) Example of an actual transfer curve (2) The ideal transfer curve (3) End point correlation line 4095 4094 4093 (2) ET (3) 7 (1) 6 5 EO EL 4 3 ED 2 1 LSB IDEAL 1 0 1 2 3 4 5 6 7 ET = total unajusted error: maximum deviation between the actual and ideal transfer curves. EO = offset error: maximum deviation between the first actual transition and the first ideal one.
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STM32L475xx 6.3.19 Electrical characteristics Digital-to-Analog converter characteristics Table 72. DAC characteristics(1) Symbol VDDA VREF+ VREF- Parameter Analog supply voltage for DAC ON Positive reference voltage Conditions Min Typ DAC output buffer OFF (no resistive load on DAC1_OUTx pin or internal connection) 1.71 - Other modes 1.80 - DAC output buffer OFF (no resistive load on DAC1_OUTx pin or internal connection) 1.71 - Other modes 1.
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Electrical characteristics STM32L475xx Table 72.
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STM32L475xx Electrical characteristics Table 72.
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Electrical characteristics STM32L475xx Table 73. DAC accuracy(1) . Symbol Parameter DNL Differential non linearity (2) - monotonicity 10 bits INL Integral non linearity(3) Offset Offset1 OffsetCal Gain TUE TUECal SNR THD 156/204 Downloaded from Arrow.com.
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STM32L475xx Electrical characteristics Table 73. DAC accuracy(1) (continued) Symbol Parameter SINAD Signal-to-noise and distortion ratio ENOB Effective number of bits Conditions Min Typ Max DAC output buffer ON CL ≤ 50 pF, RL ≥ 5 kΩ, 1 kHz - 70.4 - DAC output buffer OFF CL ≤ 50 pF, no RL, 1 kHz - 71 - DAC output buffer ON CL ≤ 50 pF, RL ≥ 5 kΩ, 1 kHz - 11.4 - DAC output buffer OFF CL ≤ 50 pF, no RL, 1 kHz - Unit dB bits 11.5 - 1. Guaranteed by design. 2.
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Electrical characteristics 6.3.20 STM32L475xx Voltage reference buffer characteristics Table 74. VREFBUF characteristics(1) Symbol Parameter Conditions Normal mode VDDA VREFBUF_ OUT Analog supply voltage Voltage reference output Degraded mode(2) Normal mode Degraded mode(2) Min Typ Max VRS = 0 2.4 - 3.6 VRS = 1 2.8 - 3.6 VRS = 0 1.65 - 2.4 VRS = 1 1.65 - 2.8 2.048 2.049(3) (3) VRS = 0 2.046 VRS = 1 2.498(3) 2.5 2.
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STM32L475xx Electrical characteristics Table 74. VREFBUF characteristics(1) (continued) Symbol Parameter VREFBUF IDDA(VREF consumption BUF) from VDDA Conditions Min Typ Max Iload = 0 µA - 16 25 Iload = 500 µA - 18 30 Iload = 4 mA - 35 50 Unit µA 1. Guaranteed by design, unless otherwise specified. 2. In degraded mode, the voltage reference buffer can not maintain accurately the output voltage which will follow (VDDA drop voltage). 3. Guaranteed by test in production. 4.
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Electrical characteristics 6.3.21 STM32L475xx Comparator characteristics Table 75. COMP characteristics(1) Symbol Conditions Min Typ Max Analog supply voltage - 1.62 - 3.6 Comparator input voltage range - 0 - VDDA V VBG(2) Scaler input voltage - VSC Scaler offset voltage - VDDA VIN IDDA(SCALER) Parameter VREFINT - ±5 ±10 mV BRG_EN=0 (bridge disable) - 200 300 nA BRG_EN=1 (bridge enable) - 0.8 1 µA - 100 200 µs VDDA ≥ 2.7 V - - 5 VDDA < 2.
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STM32L475xx Electrical characteristics Table 75.
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Electrical characteristics STM32L475xx Table 76.
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STM32L475xx Electrical characteristics Table 76.
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Electrical characteristics STM32L475xx Table 76.
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STM32L475xx 6.3.23 Electrical characteristics Temperature sensor characteristics Table 77. TS characteristics Symbol Parameter TL(1) Min Typ Max Unit - ±1 ±2 °C 2.3 2.5 2.7 mV/°C 0.742 0.76 0.
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Electrical characteristics 6.3.25 STM32L475xx DFSDM characteristics Unless otherwise specified, the parameters given in Table 80 for DFSDM are derived from tests performed under the ambient temperature, fAPB2 frequency and VDD supply voltage conditions summarized in Table 23: General operating conditions. • Output speed is set to OSPEEDRy[1:0] = 10 • Capacitive load C = 30 pF • Measurement points are done at CMOS levels: 0.5 ₓ VDD Refer to Section 6.3.
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STM32L475xx Electrical characteristics ')6'0B &.,1,1\ ')6'0B'$7$,1\ 63, WLPLQJ 63,&.6(/ Figure 16: DFSDM timing diagram WZO WZK WU WI 63,&.6(/ WVX WK 6,73 WVX WK 6,73 ')6'0B&.287 63,&.6(/ WZO WU WZK WI 63,&.6(/ ')6'0B'$7$,1\ WVX ')6'0B'$7$,1\ 0DQFKHVWHU WLPLQJ 63, WLPLQJ 63,&.6(/ 63,&.6(/ WK 6,73 WVX WK 6,73 6,73 6,73 5HFRYHUHG FORFN 5HFRYHUHG GDWD 06Y 9 6.3.
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Electrical characteristics STM32L475xx Table 81. TIMx(1) characteristics Symbol tres(TIM) Parameter Timer resolution time Conditions Min Max Unit - 1 - tTIMxCLK fTIMxCLK = 80 MHz 12.5 - ns 0 fTIMxCLK/2 MHz 0 40 MHz TIMx (except TIM2 and TIM5) - 16 TIM2 and TIM5 - 32 - 1 65536 tTIMxCLK fTIMxCLK = 80 MHz 0.0125 819.2 µs - - 65536 × 65536 tTIMxCLK fTIMxCLK = 80 MHz - 53.
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STM32L475xx 6.3.27 Electrical characteristics Communication interfaces characteristics I2C interface characteristics The I2C interface meets the timings requirements of the I2C-bus specification and user manual rev. 03 for: • Standard-mode (Sm): with a bit rate up to 100 kbit/s • Fast-mode (Fm): with a bit rate up to 400 kbit/s • Fast-mode Plus (Fm+): with a bit rate up to 1 Mbit/s.
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Electrical characteristics STM32L475xx SPI characteristics Unless otherwise specified, the parameters given in Table 85 for SPI are derived from tests performed under the ambient temperature, fPCLKx frequency and supply voltage conditions summarized in Table 23: General operating conditions. • Output speed is set to OSPEEDRy[1:0] = 11 • Capacitive load C = 30 pF • Measurement points are done at CMOS levels: 0.5 ₓ VDD Refer to Section 6.3.
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STM32L475xx Electrical characteristics Table 85. SPI characteristics(1) (continued) Symbol tv(SO) Parameter Data output valid time tv(MO) th(SO) Data output hold time th(MO) Conditions Min Typ Max Slave mode 2.7 < VDD < 3.6 V Voltage Range 1 - 12.5 19 Slave mode 1.71 < VDD < 3.6 V Voltage Range 1 - 12.5 30 Slave mode 1.71 < VDD < 3.6 V Voltage Range 2 - 12.5 33 Master mode - 2.5 12.5 Slave mode 9 - - Master mode 0 - - Unit ns ns 1.
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Electrical characteristics STM32L475xx Figure 27. SPI timing diagram - slave mode and CPHA = 1 NSS input tc(SCK) tsu(NSS) tw(SCKH) ta(SO) tw(SCKL) tf(SCK) th(NSS) SCK input CPHA=1 CPOL=0 CPHA=1 CPOL=1 tv(SO) th(SO) First bit OUT MISO output tsu(SI) MOSI input Next bits OUT tr(SCK) tdis(SO) Last bit OUT th(SI) First bit IN Next bits IN Last bit IN MSv41659V1 1. Measurement points are done at CMOS levels: 0.3 VDD and 0.7 VDD. Figure 28.
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STM32L475xx Electrical characteristics Quad SPI characteristics Unless otherwise specified, the parameters given in Table 86 and Table 87 for Quad SPI are derived from tests performed under the ambient temperature, fAHB frequency and VDD supply voltage conditions summarized in Table 23: General operating conditions, with the following configuration: • Output speed is set to OSPEEDRy[1:0] = 11 • Capacitive load C = 15 or 20 pF • Measurement points are done at CMOS levels: 0.5 ₓ VDD Refer to Section 6.3.
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Electrical characteristics STM32L475xx Table 87. QUADSPI characteristics in DDR mode(1) Symbol Parameter FCK 1/t(CK) Quad SPI clock frequency tw(CKH) Quad SPI clock high and low time tw(CKL) tsf(IN);tsr(IN) Data input setup time thf(IN); thr(IN) Data input hold time tvf(OUT);tvr(OUT) Data output valid time thf(OUT); thr(OUT) Data output hold time Conditions Min Typ Max 1.71 < VDD < 3.6 V, CLOAD = 20 pF Voltage Range 1 - - 40 2 < VDD < 3.
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STM32L475xx Electrical characteristics SAI characteristics Unless otherwise specified, the parameters given in Table 88 for SAI are derived from tests performed under the ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized inTable 23: General operating conditions, with the following configuration: • Output speed is set to OSPEEDRy[1:0] = 10 • Capacitive load C = 30 pF • Measurement points are done at CMOS levels: 0.5 ₓ VDD Refer to Section 6.3.
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Electrical characteristics STM32L475xx Table 88. SAI characteristics(1) (continued) Symbol tv(SD_B_ST) th(SD_B_ST) tv(SD_A_MT) th(SD_A_MT) Parameter Conditions Data output valid time Data output hold time Data output valid time Data output hold time Min Max Slave transmitter (after enable edge) 2.7 ≤ VDD ≤ 3.6 - 22 Slave transmitter (after enable edge) 1.71 ≤ VDD ≤ 3.6 - 34 Slave transmitter (after enable edge) 10 - Master transmitter (after enable edge) 2.7 ≤ VDD ≤ 3.
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STM32L475xx Electrical characteristics Figure 32.
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Electrical characteristics STM32L475xx Table 89. SD / MMC dynamic characteristics, VDD=2.7 V to 3.6 V(1) (continued) Symbol Parameter Conditions Min Typ Max Unit CMD, D outputs (referenced to CK) in SD default mode tOVD Output valid default time SD fPP = 50 MHz - 4.5 5 ns tOHD Output hold default time SD fPP = 50 MHz 0 - - ns 1. Guaranteed by characterization results. Table 90. eMMC dynamic characteristics, VDD = 1.71 V to 1.
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STM32L475xx Electrical characteristics Figure 34. SD default mode CK tOVD tOHD D, CMD (output) ai14888 USB OTG full speed (FS) characteristics The STM32L475xx USB interface is fully compliant with the USB specification version 2.0 and is USB-IF certified (for Full-speed device operation). Table 91. USB OTG DC electrical characteristics Symbol Parameter Conditions Min(1) Typ Max(1) Unit VDDUSB USB OTG full speed transceiver operating voltage - 3.0(2) - 3.
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Electrical characteristics STM32L475xx Figure 35. USB OTG timings – definition of data signal rise and fall time Cross over points Differential data lines VCRS VSS tf tr ai14137b Table 92.
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STM32L475xx Electrical characteristics Table 93. USB BCD DC electrical characteristics(1) (continued) Symbol Parameter Conditions Min. Typ. Max. Unit VDAT_REF Data detect voltage - 0.25 - 0.4 V VDP_SRC D+ source voltage - 0.5 - 0.7 V VDM_SRC D- source voltage - 0.5 - 0.7 V IDP_SINK D+ sink current - 25 - 175 μA IDM_SINK D- sink current - 25 - 175 μA 1. Guaranteed by design. CAN (controller area network) interface Refer to Section 6.3.
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Electrical characteristics 6.3.28 STM32L475xx FSMC characteristics Unless otherwise specified, the parameters given in Table 94 to Table 99 for the FMC interface are derived from tests performed under the ambient temperature, fHCLK frequency and VDD supply voltage conditions summarized in Table 23, with the following configuration: • Output speed is set to OSPEEDRy[1:0] = 11 • Capacitive load C = 30 pF • Measurement points are done at CMOS levels: 0.5VDD Refer to Section 6.3.
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STM32L475xx Electrical characteristics Figure 36. Asynchronous multiplexed PSRAM/NOR read waveforms tw(NE) FMC_ NE tv(NOE_NE) t h(NE_NOE) FMC_NOE t w(NOE) FMC_NWE th(A_NOE) tv(A_NE) FMC_ A[25:16] Address tv(BL_NE) th(BL_NOE) FMC_ NBL[1:0] NBL th(Data_NE) tsu(Data_NE) t v(A_NE) FMC_ AD[15:0] tsu(Data_NOE) th(Data_NOE) Data Address th(AD_NADV) t v(NADV_NE) tw(NADV) FMC_NADV FMC_NWAIT th(NE_NWAIT) tsu(NWAIT_NE) MS32755V1 DS10969 Rev 5 183/204 190 Downloaded from Arrow.com.
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Electrical characteristics STM32L475xx Table 94. Asynchronous multiplexed PSRAM/NOR read timings(1)(2) Symbol tw(NE) tv(NOE_NE) tw(NOE) th(NE_NOE) tv(A_NE) Parameter Min Max FMC_NE low time 3THCLK-0.5 3THCLK+2 FMC_NEx low to FMC_NOE low 2THCLK-0.5 2THCLK+0.5 FMC_NOE low time THCLK+0.5 THCLK+1 FMC_NOE high to FMC_NE high hold time 0 - FMC_NEx low to FMC_A valid - 3 0 1 THCLK-0.
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STM32L475xx Electrical characteristics Figure 37. Asynchronous multiplexed PSRAM/NOR write waveforms tw(NE) FMC_ NEx FMC_NOE tv(NWE_NE) tw(NWE) t h(NE_NWE) FMC_NWE th(A_NWE) tv(A_NE) FMC_ A[25:16] Address tv(BL_NE) th(BL_NWE) FMC_ NBL[1:0] NBL t v(A_NE) FMC_ AD[15:0] t v(Data_NADV) Address th(Data_NWE) Data th(AD_NADV) t v(NADV_NE) tw(NADV) FMC_NADV FMC_NWAIT th(NE_NWAIT) tsu(NWAIT_NE) MS32756V1 DS10969 Rev 5 185/204 190 Downloaded from Arrow.com.
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Electrical characteristics STM32L475xx Table 96. Asynchronous multiplexed PSRAM/NOR write timings(1)(2) Symbol Min Max FMC_NE low time 4THCLK-0.5 4THCLK+2 FMC_NEx low to FMC_NWE low THCLK-0.5 THCLK+1 2xTHCLK-1.5 2xTHCLK+1. 5 THCLK-0.5 - FMC_NEx low to FMC_A valid - 3 FMC_NEx low to FMC_NADV low 0 1 THCLK-0.
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STM32L475xx Electrical characteristics In all timing tables, the THCLK is the HCLK clock period. Figure 38.
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Electrical characteristics STM32L475xx Table 98. Synchronous multiplexed NOR/PSRAM read timings(1)(2) Symbol Min Max 2THCLK-1 - - 2 THCLK+0.5 - td(CLKL-NADVL) FMC_CLK low to FMC_NADV low - 2.5 td(CLKL-NADVH) FMC_CLK low to FMC_NADV high 1 - - 3.5 THCLK - - 1.5 THCLK+1 - tw(CLK) Parameter FMC_CLK period td(CLKL-NExL) FMC_CLK low to FMC_NEx low (x=0..
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STM32L475xx Electrical characteristics Figure 39.
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Electrical characteristics STM32L475xx Table 99. Synchronous multiplexed PSRAM write timings(1)(2) Symbol Parameter tw(CLK) FMC_CLK period Min Max 2THCLK-1 - - 2 THCLK+0.5 - td(CLKL-NExL) FMC_CLK low to FMC_NEx low (x=0..2) td(CLKH-NExH) FMC_CLK high to FMC_NEx high (x= 0…2) td(CLKL-NADVL) FMC_CLK low to FMC_NADV low - 2.5 td(CLKL-NADVH) FMC_CLK low to FMC_NADV high 1 - td(CLKL-AV) FMC_CLK low to FMC_Ax valid (x=16…25) - 3.
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STM32L475xx 7 Package information Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. 7.1 LQFP100 package information Figure 40. LQFP - 100 pins, 14 x 14 mm low-profile quad flat package outline 0.
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Package information STM32L475xx Table 101. LQFP - 100 pins, 14 x 14 mm low-profile quad flat package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A - - 1.600 - - 0.0630 A1 0.050 - 0.150 0.0020 - 0.0059 A2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 D 15.800 16.000 16.200 0.6220 0.6299 0.6378 D1 13.800 14.000 14.200 0.5433 0.5512 0.5591 D3 - 12.000 - - 0.
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STM32L475xx Package information Figure 41. LQFP - 100 pins, 14 x 14 mm low-profile quad flat recommended footprint 75 76 51 50 0.5 0.3 16.7 14.3 100 26 1.2 1 25 12.3 16.7 ai14906c 1. Dimensions are expressed in millimeters. Device marking The following figure gives an example of topside marking orientation versus pin 1 identifier location. The printed markings may differ depending on the supply chain.
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Package information STM32L475xx Figure 42. LQFP100 marking (package top view) Product identification(1) STM32L475 VGT6 Optional gate mark 3 Revision code Date code Y WW Pin 1 indentifier MSv37698V1 1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use.
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STM32L475xx 7.2 Package information LQFP64 package information Figure 43. LQFP - 64 pins, 10 x 10 mm low-profile quad flat package outline 0.25 mm GAUGE PLANE c A1 A A2 SEATING PLANE C A1 ccc C D D1 D3 K L L1 33 48 32 49 64 PIN 1 IDENTIFICATION E E1 E3 b 17 16 1 e 5W_ME_V3 1. Drawing is not to scale. Table 102. LQFP - 64 pins, 10 x 10 mm low-profile quad flat package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A - - 1.600 - - 0.0630 A1 0.
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Package information STM32L475xx Table 102. LQFP - 64 pins, 10 x 10 mm low-profile quad flat package mechanical data (continued) inches(1) millimeters Symbol Min Typ Max Min Typ Max E3 - 7.500 - - 0.2953 - e - 0.500 - - 0.0197 - K 0° 3.5° 7° 0° 3.5° 7° L 0.450 0.600 0.750 0.0177 0.0236 0.0295 L1 - 1.000 - - 0.0394 - ccc - - 0.080 - - 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 44.
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STM32L475xx Package information Figure 45. LQFP64 marking (package top view) Revision code 3 Product identification(1) STM32L475 RGT6 Y WW Date code Pin 1 identifier MSv38000V2 1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use.
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Package information 7.3 STM32L475xx Thermal characteristics The maximum chip junction temperature (TJmax) must never exceed the values given in Table 22: General operating conditions.
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STM32L475xx Package information Example 1: High-performance application Assuming the following application conditions: Maximum ambient temperature TAmax = 82 °C (measured according to JESD51-2), IDDmax = 50 mA, VDD = 3.5 V, maximum 20 I/Os used at the same time in output at low level with IOL = 8 mA, VOL= 0.4 V and maximum 8 I/Os used at the same time in output at low level with IOL = 20 mA, VOL= 1.3 V PINTmax = 50 mA × 3.5 V= 175 mW PIOmax = 20 × 8 mA × 0.4 V + 8 × 20 mA × 1.
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Package information STM32L475xx Refer to Figure 46 to select the required temperature range (suffix 6 or 7) according to your ambient temperature or power requirements. Figure 46. LQFP64 PD max vs. TA 700 PD (mW) 600 500 400 Suffix 6 300 Suffix 7 200 100 0 65 75 85 95 105 TA (°C) 200/204 Downloaded from Arrow.com.
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STM32L475xx 8 Ordering information Ordering information Table 104.
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Revision history 9 STM32L475xx Revision history Table 105. Document revision history Date Revision 05-Feb-2016 1 Initial release. 2 Removed NAND from supported memories on cover page. Added ADC 3 impacting: Cover page Section 2: Description. Table 2: STM32L475xx family device features and peripheral counts. Table 5: Functionalities depending on the working mode. Section 3.15.1: Temperature sensor. Section 3.15.3: VBAT battery voltage monitoring. Table 16: STM32L475xx pin definitions.
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STM32L475xx Revision history Table 105. Document revision history (continued) Date 09-Oct-2017 23-Apr-2018 26-Mar-2019 Revision Changes 3 (continued) Updated Table 60: I/O static characteristics. Added footnote to Figure 22: Recommended NRST pin protection. Added Section 6.3.16: Extended interrupt and event controller input (EXTI) characteristics. Updated Table 65: Analog switches booster characteristics. Updated Section 6.3.18: Analog-to-Digital converter characteristics. Updated Section 6.3.
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STM32L475xx IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.