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This is information on a product in full production.

May 2017 DocID029968 Rev 3 1/210

STM32L452xx

Ultra-low-power ARM

Cortex

-M4 32-bit MCU+FPU, 100DMIPS,

up to 512KB Flash, 160KB SRAM, analog, audio, ext. SMPS

Datasheet - production data

Features

• Ultra-low-power with FlexPowerControl

– 1.71 V to 3.6 V power supply

– -40 °C to 85/125 °C temperature range

– 145 nA in V

BAT

mode: supply for RTC and

32x32-bit backup registers

– 22 nA Shutdown mode (5 wakeup pins)

– 106 nA Standby mode (5 wakeup pins)

– 375 nA Standby mode with RTC

– 2.05 µA Stop 2 mode, 2.40 µA with RTC

– 84 µA/MHz run mode (LDO Mode)

–36 A/MHz run mode (@3.3 V SMPS

Mode)

– Batch acquisition mode (BAM)

– 4 µs wakeup from Stop mode

– Brown out reset (BOR)

– Interconnect matrix

• Core: ARM

32-bit Cortex

-M4 CPU with FPU,

Adaptive real-time accelerator (ART

Accelerator™) allowing 0-wait-state execution

from Flash memory, frequency up to 80 MHz,

MPU, 100DMIPS and DSP instructions

• Performance benchmark

– 1.25 DMIPS/MHz (Drystone 2.1)

– 273.55 CoreMark

(3.42 CoreMark/MHz @

80 MHz)

• Energy benchmark

– 245 ULPBench

score

• Clock Sources

– 4 to 48 MHz crystal oscillator

– 32 kHz crystal oscillator for RTC (LSE)

– Internal 16 MHz factory-trimmed RC (±1%)

– Internal low-power 32 kHz RC (±5%)

– Internal multispeed 100 kHz to 48 MHz

oscillator, auto-trimmed by LSE (better than

±0.25 % accuracy)

– Internal 48 MHz with clock recovery

– 2 PLLs for system clock, audio, ADC

• Up to 83 fast I/Os, most 5 V-tolerant

• RTC with HW calendar, alarms and calibration

• Up to 21 capacitive sensing channels: support

touchkey, linear and rotary touch sensors

• 12x timers: 1x 16-bit advanced motor-control,

1x 32-bit and 3x 16-bit general purpose, 2x 16-

bit basic, 2x low-power 16-bit timers (available

in Stop mode), 2x watchdogs, SysTick timer

• Memories

– Up to 512 KB single bank Flash,

proprietary code readout protection

– 160 KB of SRAM including 32 KB with

hardware parity check

– Quad SPI memory interface

• Rich analog peripherals (independent supply)

– 1× 12-bit ADC 5 Msps, up to 16-bit with

hardware oversampling, 200 µA/Msps

– 1x 12-bit DAC, low-power sample and hold

– 1x operational amplifier with built-in PGA

– 2x ultra-low-power comparators

– Accurate 2.5 V or 2.048 V reference

voltage buffered output

• 17x communication interfaces

– USB 2.0 full-speed crystal less solution

with LPM and BCD

– 1x SAI (serial audio interface)

–4x I2C FM+(1 Mbit/s), SMBus/PMBus

– 3x USARTs (ISO 7816, LIN, IrDA, modem)

– 1x UART (LIN, IrDA, modem)

–1x LPUART

– 3x SPIs (4x SPIs with the Quad SPI)

– CAN (2.0B Active) and SDMMC interface

– IRTIM (Infrared interface)

UFBGA100 (7×7)

LQFP64 (10x10)

UFBGA64 (5x5)

LQFP100 (14x14)

WLCSP64

UFQFPN48 (7x7)

www.st.com

Downloaded from Arrow.com.

Summary of content (210 pages)

PAGE 1
STM32L452xx Ultra-low-power ARM® Cortex®-M4 32-bit MCU+FPU, 100DMIPS, up to 512KB Flash, 160KB SRAM, analog, audio, ext. SMPS Datasheet - production data Features • Ultra-low-power with FlexPowerControl – 1.71 V to 3.6 V power supply – -40 °C to 85/125 °C temperature range – 145 nA in VBAT mode: supply for RTC and 32x32-bit backup registers – 22 nA Shutdown mode (5 wakeup pins) – 106 nA Standby mode (5 wakeup pins) – 375 nA Standby mode with RTC – 2.05 µA Stop 2 mode, 2.
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STM32L452xx • 14-channel DMA controller • True random number generator Reference STM32L452xx 2/210 Downloaded from Arrow.com. • CRC calculation unit, 96-bit unique ID • Development support: serial wire debug (SWD), JTAG, Embedded Trace Macrocell™ Table 1.
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STM32L452xx Contents Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.1 ARM® Cortex®-M4 core with FPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.
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Contents STM32L452xx 3.17 Voltage reference buffer (VREFBUF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.18 Comparators (COMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3.19 Operational amplifier (OPAMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3.20 Touch sensing controller (TSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3.21 Digital filter for Sigma-Delta Modulators (DFSDM) . . . . . . . .
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STM32L452xx 6.1 Contents Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 6.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 6.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 6.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 6.1.4 Loading capacitor . . . . . . . . . . . . . .
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Contents 7 STM32L452xx Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 7.1 LQFP100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 7.2 UFBGA100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 7.3 LQFP64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 7.4 UFBGA64 package information . . . . . . . . . . . . . . . . . . . . . . . .
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STM32L452xx List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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List of tables Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45. Table 46. Table 47. Table 48. Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. Table 62. Table 63. Table 64. Table 65. Table 66. Table 67. Table 68. Table 69. Table 70. Table 71. Table 72. Table 73. Table 74. Table 75. Table 76. Table 77. Table 78. Table 79. Table 80. Table 81. 8/210 Downloaded from Arrow.com.
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STM32L452xx Table 82. Table 83. Table 84. Table 85. Table 86. Table 87. Table 88. Table 89. Table 90. Table 91. Table 92. Table 93. Table 94. Table 95. Table 96. Table 97. Table 98. Table 99. Table 100. Table 101. Table 102. Table 103. Table 104. Table 105. Table 106. Table 107. Table 108. Table 109. Table 110. Table 111. Table 112. List of tables DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 DAC accuracy . . . . . . . . .
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List of figures STM32L452xx List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42. Figure 43.
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STM32L452xx Figure 45. Figure 46. Figure 47. Figure 48. Figure 49. Figure 50. Figure 51. Figure 52. Figure 53. Figure 54. Figure 55. Figure 56. Figure 57. Figure 58. List of figures UFBGA100 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package outline . . . . . . . . . . . . . . . . 193 LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package recommended footprint . . . . . . . . . . . . . . . .
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Introduction 1 STM32L452xx Introduction This datasheet provides the ordering information and mechanical device characteristics of the STM32L452xx microcontrollers. This document should be read in conjunction with the STM32L43xxx/44xxx/45xxx/46xxx reference manual (RM0394). The reference manual is available from the STMicroelectronics website www.st.com. For information on the ARM® Cortex®-M4 core, please refer to the Cortex®-M4 Technical Reference Manual, available from the www.arm.com website.
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STM32L452xx 2 Description Description The STM32L452xx devices are the ultra-low-power microcontrollers based on the highperformance ARM® Cortex®-M4 32-bit RISC core operating at a frequency of up to 80 MHz. The Cortex-M4 core features a Floating point unit (FPU) single precision which supports all ARM single-precision data-processing instructions and data types. It also implements a full set of DSP instructions and a memory protection unit (MPU) which enhances application security.
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Description STM32L452xx Table 2. STM32L452xx family device features and peripheral counts Peripheral Flash memory STM32L452Vx 256KB STM32L452Rx 512KB 256KB SRAM Timers Comm.
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STM32L452xx Description Table 2. STM32L452xx family device features and peripheral counts (continued) Peripheral STM32L452Vx STM32L452Rx Operating voltage 1.71 to 3.6 V Ambient operating temperature: -40 to 85 °C / -40 to 125 °C Junction temperature: -40 to 105 °C / -40 to 130 °C Operating temperature Packages 1. STM32L452Cx LQFP100 UFBGA100 WLCSP64 LQFP64 UFBGA64 UFQFPN48 WKUP5, ADC1_IN14 and SDMMC interface are not supported by 64-pin packages with SMPS option. 2.
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Description STM32L452xx Figure 1. STM32L452xx block diagram ' > @ ' > @ &/. &/. &6 1-7567 -7', -7&. 6:&/. 4XDG 63, PHPRU\ LQWHUIDFH -7$* 6: 038 (70 19,& -7'2 6:' -7'2 75$&(&/. ' %86 75$&('> @ $50 &RUWH[ 0 0+] )38 , %86 $57 $&&(/ &$&+( 51* )ODVK XS WR .% $+% EXV PDWUL[ 6 %86 65$0 .% 65$0 .
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STM32L452xx Functional overview 3 Functional overview 3.1 ARM® Cortex®-M4 core with FPU The ARM® Cortex®-M4 with FPU processor is the latest generation of ARM processors for embedded systems. It was developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced response to interrupts.
PAGE 18
Functional overview 3.4 STM32L452xx Embedded Flash memory STM32L452xx devices feature up to 512 Kbyte of embedded Flash memory available for storing programs and data in single bank architecture. The Flash memory contains 256 pages of 2 Kbyte. Flexible protections can be configured thanks to option bytes: • Readout protection (RDP) to protect the whole memory.
PAGE 19
STM32L452xx Functional overview The whole non-volatile memory embeds the error correction code (ECC) feature supporting: 3.5 • single error detection and correction • double error detection. • The address of the ECC fail can be read in the ECC register Embedded SRAM STM32L452xx devices feature 160 Kbyte of embedded SRAM. This SRAM is split into two blocks: • 128 Kbyte mapped at address 0x2000 0000 (SRAM1) • 32 Kbyte located at address 0x1000 0000 with hardware parity check (SRAM2).
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Functional overview 3.7 STM32L452xx Boot modes At startup, BOOT0 pin or nSWBOOT0 option bit, and BOOT1 option bit are used to select one of three boot options: • Boot from user Flash • Boot from system memory • Boot from embedded SRAM BOOT0 value may come from the PH3-BOOT0 pin or from an option bit depending on the value of a user option bit to free the GPIO pad if needed.
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STM32L452xx Functional overview Note: If these supplies are tied to ground, the I/Os supplied by these power supplies are not 5 V tolerant. Note: VDDIOx is the I/Os general purpose digital functions supply. VDDIOx represents VDDIO1, with VDDIO1 = VDD. Figure 2.
PAGE 22
Functional overview 3.9.3 STM32L452xx Voltage regulator Two embedded linear voltage regulators supply most of the digital circuitries: the main regulator (MR) and the low-power regulator (LPR). • The MR is used in the Run and Sleep modes and in the Stop 0 mode. • The LPR is used in Low-Power Run, Low-Power Sleep, Stop 1 and Stop 2 modes. It is also used to supply the 32 Kbyte SRAM2 in Standby with SRAM2 retention.
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Downloaded from Arrow.com. DocID029968 Rev 3 Stop 0 LPSleep Sleep LPRun Run Mode MR Range 2(8) MR Range 1(8) LPR SMPS range 2 Low MR range2 SMPS range 2 High MR range 1 LPR SMPS range 2 Low MR range2 SMPS range 2 High MR range 1 Regulator(1) No No No Yes Yes CPU OFF ON(6) ON(6) ON(6) ON(6) ON ON(7) ON(7) ON ON LSE LSI Any except PLL Any Any except PLL Any Flash SRAM Clocks Any interrupt or event Reset pin, all I/Os BOR, PVD, PVM RTC, IWDG COMPx (x=1..
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/210 Downloaded from Arrow.com. LPR LPR Stop 1 Stop 2 Regulator Mode (1) No No CPU Off Off ON ON Reset pin, all I/Os BOR, PVD, PVM RTC, IWDG COMPx (x=1..2) USARTx (x=1...3)(9) UART4(9) LPUART1(9) I2Cx (x=1...4)(10) LPTIMx (x=1,2) USB_FS(11) BOR, PVD, PVM RTC, IWDG COMPx (x=1,2) DAC1 OPAMPx (x=1) USARTx (x=1...3)(9) UART4(9) LPUART1(9) I2Cx (x=1...4)(10) LPTIMx (x=1,2) *** All other peripherals are frozen. BOR, PVD, PVM RTC, IWDG COMPx (x=1..
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Downloaded from Arrow.com. OFF OFF LPR Regulator Power ed Off Power ed Off CPU Reset pin 5 I/Os (WKUPx)(12) RTC RTC *** All other peripherals are powered off. *** I/O configuration can be floating, pull-up or pulldown(13) Off Power ed Off Power ed Off Reset pin 5 I/Os (WKUPx)(12) BOR, RTC, IWDG LSE LSE LSI BOR, RTC, IWDG *** All other peripherals are powered off.
PAGE 26
Functional overview STM32L452xx By default, the microcontroller is in Run mode after a system or a power Reset. It is up to the user to select one of the low-power modes described below: • Sleep mode In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can wake up the CPU when an interrupt/event occurs. • Low-power run mode This mode is achieved with VCORE supplied by the low-power regulator to minimize the regulator's operating current.
PAGE 27
STM32L452xx • Functional overview Shutdown mode The Shutdown mode allows to achieve the lowest power consumption. The internal regulator is switched off so that the VCORE domain is powered off. The PLL, the HSI16, the MSI, the LSI and the HSE oscillators are also switched off. The RTC can remain active (Shutdown mode with RTC, Shutdown mode without RTC). The BOR is not available in Shutdown mode. No power voltage monitoring is possible in this mode, therefore the switch to Backup domain is not supported.
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Functional overview STM32L452xx Table 5.
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STM32L452xx Functional overview Table 5.
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Functional overview STM32L452xx Table 5. Functionalities depending on the working mode(1) (continued) - - - CRC calculation unit O O O O - - - - - - - - - GPIOs O O O O O O O O (9) 5 pins (11) 5 pins - Peripheral Run Sleep Lowpower run Lowpower sleep - (10) Wakeup capability Shutdown Wakeup capability Standby Wakeup capability Stop 2 Wakeup capability Stop 0/1 VBAT (10) 1. Legend: Y = Yes (Enable). O = Optional (Disable by default.
PAGE 31
STM32L452xx 3.10 Functional overview Interconnect matrix Several peripherals have direct connections between them. This allows autonomous communication between peripherals, saving CPU resources thus power supply consumption. In addition, these hardware connections allow fast and predictable latency. Depending on peripherals, these interconnections can operate in Run, Sleep, low-power run and sleep, Stop 0, Stop 1 and Stop 2 modes.
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Functional overview STM32L452xx Sleep Low-power run Low-power sleep Stop 0 / Stop 1 Stop 2 Interconnect source Run Table 6. STM32L452xx peripherals interconnect matrix (continued) TIMx External trigger Y Y Y Y - - LPTIMERx External trigger Y Y Y Y Y (1) ADCx DACx Conversion external trigger Y Y Y Y - - Interconnect destination Interconnect action Y GPIO 1. LPTIM1 only. 32/210 Downloaded from Arrow.com.
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STM32L452xx 3.11 Functional overview Clocks and startup The clock controller (see Figure 3) distributes the clocks coming from different oscillators to the core and the peripherals. It also manages clock gating for low-power modes and ensures clock robustness.
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Functional overview STM32L452xx interrupt is generated if enabled. LSE failure can also be detected and generated an interrupt. • Clock-out capability: – MCO: microcontroller clock output: it outputs one of the internal clocks for external use by the application – LSCO: low speed clock output: it outputs LSI or LSE in all low-power modes (except VBAT). Several prescalers allow to configure the AHB frequency, the high speed APB (APB2) and the low speed APB (APB1) domains.
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STM32L452xx Functional overview Figure 3. Clock tree WR ,:'* >^/ Z ϯϮ Ŭ,ǌ /6&2 WR 57& 26& B287 >^ K^ ϯϮ͘ϳϲϴ Ŭ,ǌ ͬϯϮ 26& B,1 /6( /6, +6( 0&2 ĺ WR 3:5 6<6&/. +6, 26&B287 ,^ K^ ϰͲϰϴ D,ǌ 26&B,1 ůŽĐŬ ĚĞƚĞĐƚŽƌ WR $+% EXV FRUH PHPRU\ DQG '0$ ůŽĐŬ ƐŽƵƌĐĞ ĐŽŶƚƌŽů +6, , WZ ^ ͬ ϭ͕Ϯ͕͘͘ϱϭϮ +6( +&/. )&/. &RUWH[ IUHH UXQQLQJ FORFN WR &RUWH[ V\VWHP WLPHU ͬ ϴ 06, +6, 6<6&/. W ϭ WZ ^ ͬ ϭ͕Ϯ͕ϰ͕ϴ͕ϭϲ 3&/. WR $3% SHULSKHUDOV ǆϭ Žƌ ǆϮ ,^/ Z ϭϲ D,ǌ /6( +6, 6<6&/.
PAGE 36
Functional overview 3.12 STM32L452xx General-purpose inputs/outputs (GPIOs) Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog alternate functions. Fast I/O toggling can be achieved thanks to their mapping on the AHB2 bus.
PAGE 37
STM32L452xx Functional overview 3.14 Interrupts and events 3.14.1 Nested vectored interrupt controller (NVIC) The devices embed a nested vectored interrupt controller able to manage 16 priority levels, and handle up to 67 maskable interrupt channels plus the 16 interrupt lines of the Cortex®M4.
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Functional overview 3.15 STM32L452xx Analog to digital converter (ADC) The device embeds a successive approximation analog-to-digital converter with the following features: • 12-bit native resolution, with built-in calibration • 5.33 Msps maximum conversion rate with full resolution Down to 18.75 ns sampling time – Increased conversion rate for lower resolution (up to 8.88 Msps for 6-bit resolution) • Up to 16 external channels.
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STM32L452xx Functional overview Table 8. Temperature sensor calibration values 3.15.2 Calibration value name Description Memory address TS_CAL1 TS ADC raw data acquired at a temperature of 30 °C (± 5 °C), VDDA = VREF+ = 3.0 V (± 10 mV) 0x1FFF 75A8 - 0x1FFF 75A9 TS_CAL2 TS ADC raw data acquired at a temperature of 130 °C (± 5 °C), VDDA = VREF+ = 3.
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Functional overview STM32L452xx This digital interface supports the following features: • Up to two DAC output channels • 8-bit or 12-bit output mode • Buffer offset calibration (factory and user trimming) • Left or right data alignment in 12-bit mode • Synchronized update capability • Noise-wave generation • Triangular-wave generation • Dual DAC channel independent or simultaneous conversions • DMA capability for each channel • External triggers for conversion • Sample and hold low-p
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STM32L452xx 3.18 Functional overview Comparators (COMP) The STM32L452xx devices embed two rail-to-rail comparators with programmable reference voltage (internal or external), hysteresis and speed (low speed for low-power) and with selectable output polarity. The reference voltage can be one of the following: • External I/O • DAC output channels • Internal reference voltage or submultiple (1/4, 1/2, 3/4).
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Functional overview STM32L452xx The main features of the touch sensing controller are the following: • Proven and robust surface charge transfer acquisition principle • Supports up to 21 capacitive sensing channels • Up to 3 capacitive sensing channels can be acquired in parallel offering a very good response time • Spread spectrum feature to improve system robustness in noisy environments • Full hardware management of the charge transfer acquisition sequence • Programmable charge transfer freq
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STM32L452xx Functional overview hardware. DFSDM features optional parallel data stream inputs from microcontrollers memory (through DMA/CPU transfers into DFSDM). DFSDM transceivers support several serial interface formats (to support various Σ∆ modulators). DFSDM digital filter modules perform digital processing according user selected filter parameters with up to 24-bit final ADC resolution.
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Functional overview STM32L452xx without having any impact on the timing of “injected” conversions – “injected” conversions for precise timing and with high conversion priority Table 10. DFSDM1 implementation DFSDM features DFSDM1 Number of channels 8 Number of filters 4 Input from internal ADC - Supported trigger sources 3.
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STM32L452xx 3.23.1 Functional overview Advanced-control timer (TIM1) The advanced-control timer can each be seen as a three-phase PWM multiplexed on 6 channels. They have complementary PWM outputs with programmable inserted deadtimes. They can also be seen as complete general-purpose timers.
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Functional overview 3.23.4 STM32L452xx Low-power timer (LPTIM1 and LPTIM2) The devices embed two low-power timers. These timers have an independent clock and are running in Stop mode if they are clocked by LSE, LSI or an external clock. They are able to wakeup the system from Stop mode. LPTIM1 is active in Stop 0, Stop 1 and Stop 2 modes. LPTIM2 is active in Stop 0 and Stop 1 mode. This low-power timer supports the following features: 3.23.
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STM32L452xx 3.23.8 Functional overview SysTick timer This timer is dedicated to real-time operating systems, but could also be used as a standard down counter. It features: 3.24 • A 24-bit down counter • Autoreload capability • Maskable system interrupt generation when the counter reaches 0. • Programmable clock source Real-time clock (RTC) and backup registers The RTC is an independent BCD timer/counter.
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Functional overview 3.25 STM32L452xx Inter-integrated circuit interface (I2C) The device embeds 4 I2C. Refer to Table 12: I2C implementation for the features implementation. The I2C bus interface handles communications between the microcontroller and the serial I2C bus. It controls all I2C bus-specific sequencing, protocol, arbitration and timing. The I2C peripheral supports: • • I2C-bus specification and user manual rev.
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STM32L452xx 3.26 Functional overview Universal synchronous/asynchronous receiver transmitter (USART) The STM32L452xx devices have three embedded universal synchronous receiver transmitters (USART1, USART2 and USART3) and one universal asynchronous receiver transmitters (UART4). These interfaces provide asynchronous communication, IrDA SIR ENDEC support, multiprocessor communication mode, single-wire half-duplex communication mode and have LIN Master/Slave capability.
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Functional overview 3.27 STM32L452xx Low-power universal asynchronous receiver transmitter (LPUART) The device embeds one Low-Power UART. The LPUART supports asynchronous serial communication with minimum power consumption. It supports half duplex single wire communication and modem operations (CTS/RTS). It allows multiprocessor communication. The LPUART has a clock domain independent from the CPU clock, and can wakeup the system from Stop mode using baudrates up to 220 Kbaud.
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STM32L452xx 3.28 Functional overview Serial peripheral interface (SPI) Three SPI interfaces allow communication up to 40 Mbits/s in master and up to 24 Mbits/s slave modes, in half-duplex, full-duplex and simplex modes. The 3-bit prescaler gives 8 master mode frequencies and the frame size is configurable from 4 bits to 16 bits. The SPI interfaces support NSS pulse mode, TI mode and Hardware CRC calculation. All SPI interfaces can be served by the DMA controller. 3.
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Functional overview STM32L452xx Table 14. SAI implementation SAI features Support(1) I2S, LSB or MSB-justified, PCM/DSP, TDM, AC’97 X Mute mode X Stereo/Mono audio frame capability. X 16 slots X Data size configurable: 8-, 10-, 16-, 20-, 24-, 32-bit X FIFO Size X (8 Word) SPDIF X 1. X: supported 3.30 Controller area network (CAN) The CAN is compliant with specifications 2.0A and B (active) with a bit rate up to 1 Mbit/s.
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STM32L452xx Functional overview The SDMMC features include the following: 3.32 • Full compliance with MultiMediaCard System Specification Version 4.2. Card support for three different databus modes: 1-bit (default), 4-bit and 8-bit • Full compatibility with previous versions of MultiMediaCards (forward compatibility) • Full compliance with SD Memory Card Specifications Version 2.0 • Full compliance with SD I/O Card Specification Version 2.
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Functional overview STM32L452xx The Quad SPI interface supports: 54/210 Downloaded from Arrow.com. • Three functional modes: indirect, status-polling, and memory-mapped • Dual-flash mode, where 8 bits can be sent/received simultaneously by accessing two flash memories in parallel.
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STM32L452xx Functional overview 3.35 Development support 3.35.1 Serial wire JTAG debug port (SWJ-DP) The ARM SWJ-DP interface is embedded, and is a combined JTAG and serial wire debug port that enables either a serial wire debug or a JTAG probe to be connected to the target.
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Pinouts and pin description 4 STM32L452xx Pinouts and pin description 9'' 966 3( 3( 3% 3% 3+ %227 %227 3% 3% 3% 3% 1-7567 3% -7'2 75$&(6:2 3' 3' 3' 3' 3' 3' 3' 3' 3& 3& 3& 3$ -7', 3$ -7&. 6:&/. Figure 5.
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STM32L452xx Pinouts and pin description Figure 6. STM32L452Vx UFBGA100 ballout(1) $ 3( 3( 3% 3+ %227 %227 3' 3' 3% 1-7567 3% -7'2 75$&(6:2 3$ -7', 3$ -7&. 6:&/.
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Pinouts and pin description STM32L452xx 9'' 966 9'' 3% 3% 3+ %227 %227 3% 3% 3% 3% 1-7567 3% -7'2 75$&(6:2 3& 3& 3& 3$ -7', 3$ -7&. 6:&/. Figure 8.
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STM32L452xx Pinouts and pin description Figure 10. STM32L452Rx WLCSP64 pinout(1) $ % 9''86% 3$ -7', 3& 3% 1-7567 3& 3% -7'2 75$&(6:2 966 9'' 3% 3% 966 9'' 3% 3+ %227 %227 9%$7 3& 3& 26& B,1 3& & 3$ 3$ -706 6:',2 3$ -7&. 6:&/.
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Pinouts and pin description STM32L452xx Table 15. Legend/abbreviations used in the pinout table Name Abbreviation Definition Unless otherwise specified in brackets below the pin name, the pin function during and after reset is the same as the actual pin name Pin name Pin type S Supply pin I Input only pin I/O Input / output pin FT 5 V tolerant I/O TT 3.
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STM32L452xx Pinouts and pin description Table 16.
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Pinouts and pin description STM32L452xx Table 16.
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STM32L452xx Pinouts and pin description Table 16.
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Pinouts and pin description STM32L452xx Table 16.
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STM32L452xx Pinouts and pin description Table 16.
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Pinouts and pin description STM32L452xx Table 16.
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STM32L452xx Pinouts and pin description Table 16.
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Pinouts and pin description STM32L452xx Table 16.
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STM32L452xx Pinouts and pin description Table 16.
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Pinouts and pin description STM32L452xx Table 16.
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/210 Downloaded from Arrow.com. Port H - - PH3 - SYS_AF PH1 PH0 Port AF0 - - - TIM1/TIM2 LPTIM1 AF1 - - - I2C4/TIM1/ TIM2/TIM3 AF2 - - - I2C4/USART2/ CAN1/TIM1 AF3 - - - I2C1/I2C2/ I2C3/I2C4 AF4 - - - SPI1/SPI2/I2C4 AF5 AF6 - - - SPI3/DFSDM/ COMP1 Table 17.
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Memory mapping 5 STM32L452xx Memory mapping Figure 12.
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STM32L452xx Memory mapping Table 19.
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Memory mapping STM32L452xx Table 19.
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STM32L452xx Memory mapping Table 19. STM32L452xx memory map and peripheral register boundary addresses(1) (continued) Bus APB1 Boundary address Size(bytes) Peripheral 0x4000 3000 - 0x4000 33FF 1 KB IWDG 0x4000 2C00 - 0x4000 2FFF 1 KB WWDG 0x4000 2800 - 0x4000 2BFF 1 KB RTC 0x4000 1400 - 0x4000 27FF 5 KB Reserved 0x4000 1000 - 0x4000 13FF 1 KB TIM6 0x4000 0800- 0x4000 0FFF 2 KB Reserved 0x4000 0400 - 0x4000 07FF 1 KB TIM3 0x4000 0000 - 0x4000 03FF 1 KB TIM2 1.
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Electrical characteristics STM32L452xx 6 Electrical characteristics 6.1 Parameter conditions Unless otherwise specified, all voltages are referenced to VSS. 6.1.1 Minimum and maximum values Unless otherwise specified, the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at TA = 25 °C and TA = TAmax (given by the selected temperature range).
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STM32L452xx 6.1.6 Electrical characteristics Power supply scheme Figure 15. Power supply scheme 9%$7 %DFNXS FLUFXLWU\ /6( 57& %DFNXS UHJLVWHUV ± 9 3RZHU VZLWFK 9'' 9&25( Q [ 9'' 5HJXODWRU 287 Q [ Q) *3,2V ,1 [ ) /HYHO VKLIWHU 9'',2 ,2 ORJLF .HUQHO ORJLF &38 'LJLWDO 0HPRULHV Q [ 966 9''$ 9''$ 95() Q) ) Q) ) $'& 95() '$& 23$03 95() &203V 95()%8) 966$ 06Y 9 Caution: Each power supply pair (VDD/VSS, VDDA/VSSA etc.
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Electrical characteristics 6.1.7 STM32L452xx Current consumption measurement Figure 16. Current consumption measurement scheme with and without external SMPS power supply ,''B86% ,''B86% 9''86% 9''86% ,''B9%$7 ,''B9%$7 9%$7 9%$7 ,'' ,'' ,''$ 6036 9'' 9'' 9'' ,''$ 9''$ 9''$ 06Y 9 The IDD_ALL parameters given in Table 27 to Table 49 represent the total MCU consumption including the current supplying VDD, VDDA, VDDUSB and VBAT. 6.
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STM32L452xx Electrical characteristics Table 20. Voltage characteristics(1) (continued) Symbol |∆VDDx| |VSSx-VSS| Ratings Min Max Unit Variations between different VDDX power pins of the same domain - 50 mV Variations between all the different ground pins(5) - 50 mV 1. All main power (VDD, VDDA, VDDUSB, VBAT) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the permitted range. 2. VIN maximum must always be respected.
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Electrical characteristics STM32L452xx Table 22. Thermal characteristics Symbol TSTG TJ 90/210 Downloaded from Arrow.com.
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STM32L452xx Electrical characteristics 6.3 Operating conditions 6.3.1 General operating conditions Table 23. General operating conditions Symbol Parameter Conditions Min Max fHCLK Internal AHB clock frequency - 0 80 fPCLK1 Internal APB1 clock frequency - 0 80 fPCLK2 Internal APB2 clock frequency - 0 80 VDD Standard operating voltage - VDD12 Standard operating voltage VDDA Analog supply voltage V 1.32 V 3.6 V 1.55 3.6 V 3.0 3.6 0 3.6 TT_xx I/O -0.3 VDDIOx+0.
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Electrical characteristics STM32L452xx Table 23. General operating conditions (continued) Symbol Parameter Conditions Max Ambient temperature for the suffix 6 version Maximum power dissipation –40 85 Low-power dissipation(5) –40 105 Ambient temperature for the suffix 3 version Maximum power dissipation –40 125 Low-power dissipation(5) –40 130 Suffix 6 version –40 105 Suffix 3 version –40 130 TA TJ Min Junction temperature range Unit °C °C 1.
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STM32L452xx Electrical characteristics Table 25. Embedded reset and power control block characteristics (continued) Symbol Conditions(1) Min Typ Max Rising edge 2.06 2.1 2.14 Falling edge 1.96 2 2.04 Rising edge 2.26 2.31 2.35 Falling edge 2.16 2.20 2.24 Rising edge 2.56 2.61 2.66 Falling edge 2.47 2.52 2.57 Rising edge 2.85 2.90 2.95 Falling edge 2.76 2.81 2.86 Rising edge 2.1 2.15 2.19 Falling edge 2 2.05 2.1 Rising edge 2.26 2.31 2.36 Falling edge 2.
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Electrical characteristics STM32L452xx Table 25. Embedded reset and power control block characteristics (continued) Symbol Parameter Conditions(1) Min Typ Max Unit Vhyst_PVM3 PVM3 hysteresis - - 10 - mV Vhyst_PVM4 PVM4 hysteresis - - 10 - mV PVM1 consumption from VDD - - 0.2 - µA - - 2 - µA IDD (PVM1) (2) IDD PVM3 and PVM4 (PVM3/PVM4) consumption from VDD (2) 1. Continuous mode means Run/Sleep modes, or temperature sensor enable in Low-power run/Low-power sleep modes. 2.
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STM32L452xx 6.3.4 Electrical characteristics Embedded voltage reference The parameters given in Table 26 are derived from tests performed under the ambient temperature and supply voltage conditions summarized in Table 23: General operating conditions. Table 26. Embedded internal voltage reference Symbol VREFINT Parameter Conditions Internal reference voltage –40 °C < TA < +130 °C Min Typ Max Unit 1.182 1.212 1.
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Electrical characteristics STM32L452xx Figure 17. VREFINT versus temperature 9 0HDQ 96/210 Downloaded from Arrow.com.
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STM32L452xx 6.3.5 Electrical characteristics Supply current characteristics The current consumption is a function of several parameters and factors such as the operating voltage, ambient temperature, I/O pin loading, device software configuration, operating frequencies, I/O pin switching rate, program location in memory and executed binary code. The current consumption is measured as described in Figure 16: Current consumption measurement scheme with and without external SMPS power supply.
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/210 Downloaded from Arrow.com. 2.35 1.50 0.815 0.845 26 MHz 16 MHz 8 MHz 0.295 0.320 2 MHz DocID029968 Rev 3 6.80 5.10 3.45 2.60 1.80 225 130 73.0 38.0 64 MHz Range 1 48 MHz 32 MHz 24 MHz 16 MHz 2 MHz 1 MHz 400 kHz 100 kHz 1. Guaranteed by characterization results, unless otherwise specified. 7.65 72 MHz 71.0 99.5 160 260 1.85 2.65 3.50 5.15 6.85 7.70 175 205 270 365 1.95 2.80 3.60 5.25 7.00 7.85 8.65 8.45 80 MHz 8.50 0.250 100 kHz 0.130 0.155 0.420 0.595 0.940 1.
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Downloaded from Arrow.com. DocID029968 Rev 3 Supply current in Run mode IDD_ALL(Run) fHCLK = fHSE up to 48MHz included, bypass mode PLL ON above 48 MHz all peripherals disable - Conditions(1) 0.35 0.20 0.13 0.09 0.06 4 MHz 2 MHz 1 MHz 100 kHz 1.24 32 MHz 8 MHz 1.83 48 MHz 0.65 2.44 64 MHz 16 MHz 2.75 72 MHz 0.93 3.04 80 MHz 24 MHz 25 °C fHCLK 0.07 0.10 0.14 0.21 0.36 0.67 0.95 1.26 1.85 2.46 2.77 3.06 55 °C 0.11 0.14 0.18 0.26 0.41 0.70 1.01 1.29 1.89 2.52 2.
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/210 Downloaded from Arrow.com. Supply current in fHCLK = fMSI Low-power all peripherals disable run IDD_ALL (Run) IDD_ALL (LPRun) 2.75 1.95 1.10 26 MHz 16 MHz 8 MHz 0.255 9.05 100 kHz 0.135 0.160 80 MHz DocID029968 Rev 3 7.90 6.60 4.75 3.60 2.60 340 175 89.5 42.5 Range 1 48 MHz 32 MHz 24 MHz 16 MHz 2 MHz 1 MHz 400 kHz 100 kHz 1. Guaranteed by characterization results, unless otherwise specified. 8.00 64 MHz 75.5 120 215 360 2.65 3.65 4.80 6.65 7.95 8.05 8.90 0.250 0.
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Downloaded from Arrow.com. DocID029968 Rev 3 Supply current in Run mode IDD_ALL(Run) fHCLK = fHSE up to 48MHz included, bypass mode PLL ON above 48 MHz all peripherals disable - Conditions(1) 25 °C 3.18 2.88 2.84 2.37 1.71 1.29 0.93 0.47 0.28 0.16 0.11 0.06 fHCLK 80 MHz 72 MHz 64 MHz 48 MHz 32 MHz 24 MHz 16 MHz 8 MHz 4 MHz 2 MHz 1 MHz 100 kHz 0.07 0.12 0.17 0.29 0.50 0.95 1.31 1.73 2.39 2.86 2.89 3.20 55 °C 0.11 0.16 0.22 0.33 0.54 0.99 1.37 1.78 2.44 2.91 2.95 3.25 0.18 0.
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/210 Downloaded from Arrow.com. fHCLK = fMSI all peripherals disable FLASH in power-down Supply current in low-power run mode DocID029968 Rev 3 Range 1 8.55 80 MHz 36.0 100 kHz 220 2 MHz 60.0 1.80 16 MHz 400 kHz 2.65 24 MHz 120 3.45 32 MHz 1 MHz 5.15 48 MHz 6.90 0.130 64 MHz 0.210 1 MHz 100 kHz 7.70 0.295 2 MHz 72 MHz 0.470 0.820 8 MHz 4 MHz 2.40 1.50 26 MHz 16 MHz 25 °C fHCLK 1. Guaranteed by characterization results, unless otherwise specified.
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Downloaded from Arrow.com. Parameter - Conditions(1) DocID029968 Rev 3 0.35 0.20 0.13 0.09 0.05 8 MHz 4 MHz 2 MHz 1 MHz 100 kHz 1.26 32 MHz 0.65 1.87 48 MHz 16 MHz 2.50 64 MHz 0.96 2.80 72 MHz 24 MHz 3.10 80 MHz 0.06 0.09 0.13 0.21 0.36 0.66 0.96 1.27 1.88 2.51 2.81 3.12 25 °C 55 °C fHCLK 0.07 0.11 0.15 0.22 0.38 0.68 0.98 1.29 1.90 2.53 2.84 3.14 85 °C TYP 0.10 0.14 0.18 0.25 0.41 0.71 1.02 1.32 1.93 2.57 2.87 3.18 0.16 0.20 0.24 0.31 0.47 0.
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Electrical characteristics STM32L452xx Table 33. Typical current consumption in Run and Low-power run modes, with different codes running from Flash, ART enable (Cache ON Prefetch OFF) Conditions Symbol Parameter Range 2 fHCLK = 26 MHz Code 25 °C Reduced code(1) 2.35 90 Coremark 2.65 102 Dhrystone 2.1 2.75 Fibonacci 2.60 100 2.35 90 Reduced code 8.45 106 Coremark 9.45 118 Dhrystone 2.1 9.85 Fibonacci 9.25 116 8.45 106 Reduced code 225 113 Coremark 260 130 Dhrystone 2.
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STM32L452xx Electrical characteristics 1. All values are obtained by calculation based on measurements done without SMPS and using following parameters: SMPS input = 3.3 V, SMPS efficiency = 85%, VDD12 = 1.10 V 2. Reduced code used for characterization results provided in Table 27, Table 29, Table 31. Table 35. Typical current consumption in Run, with different codes running from Flash, ART enable (Cache ON Prefetch OFF) and power supplied by external SMPS (VDD12 = 1.
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Electrical characteristics STM32L452xx Table 36.
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STM32L452xx Electrical characteristics Table 38. Typical current consumption in Run modes, with different codesrunning from Flash, ART disable and power supplied by external SMPS (VDD12 = 1.05 V) Conditions(1) IDD_ALL (Run) Parameter Supply current in Run mode TYP Voltage scaling fHCLK = fHSE up to 48 MHz included, bypass mode PLL ON above 48 MHz all peripherals fHCLK = 26 MHz Symbol Code 25 °C Reduced code(2) 1.08 TYP Unit 25 °C Unit 42 Coremark 0.98 Dhrystone 2.1 0.
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Electrical characteristics STM32L452xx Table 40. Typical current consumption in Run, with different codesrunning from SRAM1 and power supplied by external SMPS (VDD12 = 1.10 V) Conditions(1) IDD_ALL (Run) Parameter Supply current in Run mode Voltage scaling - fHCLK = fHSE up to 48 MHz included, bypass mode PLL ON above 48 MHz all peripherals disable fHCLK = 80 MHz fHCLK = 26 MHz Symbol TYP Code 25 °C Reduced code(2) 1.04 TYP Unit 25 °C Unit 40 Coremark 0.95 37 Dhrystone 2.1 1.
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Downloaded from Arrow.com. DocID029968 Rev 3 IDD_ALL (Sleep) 0.145 0.170 0.125 0.150 2.30 2.10 1.90 100 kHz 80 MHz 72 MHz 64 MHz 0.765 0.800 0.555 0.590 76.0 54.0 39.0 35.5 24 MHz 16 MHz 2 MHz 1 MHz 400 kHz 100 kHz 1.40 75.0 70.5 86.5 110 1.00 1.40 0.970 32 MHz 1.90 2.15 2.35 0.165 0.190 1 MHz 8 MHz 2 MHz 0.475 0.505 0.300 0.325 16 MHz 0.210 0.235 0.700 0.730 26 MHz 4 MHz 25 °C 55 °C fHCLK Range 1 48 MHz Range 2 Voltage scaling 1.
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/210 Downloaded from Arrow.com. Supply current in sleep mode, IDD_ALL(Sleep) fHCLK = fHSE up to 48 MHz included, bypass mode pll ON above 48 MHz all peripherals disable - Conditions(1) 0.28 0.20 0.13 0.09 24 MHz 16 MHz 8 MHz 4 MHz 0.05 0.35 32 MHz 100 kHz 0.50 48 MHz 0.07 0.68 64 MHz 0.06 0.75 72 MHz 1 MHz 0.83 80 MHz 2 MHz 25 °C fHCLK 0.06 0.07 0.08 0.10 0.14 0.21 0.29 0.36 0.50 0.68 0.77 0.84 55 °C 0.11 0.11 0.13 0.14 0.18 0.25 0.33 0.41 0.56 0.74 0.
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Downloaded from Arrow.com. IDD_ALL (Stop 2) RTC clocked by LSI - - Conditions DocID029968 Rev 3 5.90 2.10 2.05 2.05 2.30 2.35 2.4 V 3V 3.6 V 1.8 V 2.4 V 2.60 2.65 3V 3.6 V 3V 2.50 2.4 V Wakeup clock is HSI16 = 16 MHz, voltage Range 1. See (3). 2.40 1.8 V 3V 2.85 3.6 V Wakeup clock is MSI = 4 MHz, voltage Range 2. See (3). 2.80 3V 1.55 1.50 1.85 6.00 2.55 2.4 V 3V 5.85 2.60 1.8 V - - - 20.5 20.0 19.5 19.0 22.5 21.5 21.0 21.0 20.5 20.0 19.5 19.0 20.0 19.5 19.
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3. Wakeup with code execution from Flash. Average value given for a typical wakeup time as specified in Table 52: Low-power mode wakeup timings. Electrical characteristics 112/210 Downloaded from Arrow.com.
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Downloaded from Arrow.com. Supply current in Stop 1 mode, RTC disabled IDD_ALL (Stop 1) RTC clocked by LSI - - Conditions DocID029968 Rev 3 10.5 10.0 10.0 3.6 V 1.8 V 2.4 V 3.6 V 1.20 1.20 3V 3V 1.15 10.5 3V 3V 10.0 10.0 2.4 V 30.5 11.0 10.0 3.6 V 1.8 V - - - 100 100 99.5 99.
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/210 Downloaded from Arrow.com. Supply current in Stop 0 mode, RTC disabled IDD_ALL (Stop 0) 125 125 125 125 1.8 V 2.4 V 3V 3.6 V 2. Guaranteed by test in production. 155 150 150 150 25 °C 55 °C VDD Conditions 1. Guaranteed by characterization results, unless otherwise specified. Parameter Symbol 245 245 240 240 85 °C TYP 400 395 390 390 655 650 645 645 155 155 150 145 105 °C 125 °C 25 °C Table 47.
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Downloaded from Arrow.com. IDD_ALL (Standby) IDD_ALL (Standby with RTC) Supply current in Standby mode (backup registers retained), RTC disabled Supply current in Standby mode (backup registers retained), RTC enabled Parameter Symbol DocID029968 Rev 3 665 810 460 565 720 2.4 V RTC clocked by LSE quartz (2) in low drive mode 3 V 3.6 V - 1000 550 795 375 - - - 1150 860 690 540 915 745 620 505 895 655 540 435 445 360 305 1.8 V 625 3V 620 3V 500 490 2.4 V 2.4 V 375 1.
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/210 Downloaded from Arrow.com. Supply current to be added in Standby mode when SRAM2 is retained Supply current during wakeup from Standby mode Parameter Wakeup clock is MSI = 4 MHz. See (4). - - Conditions 255 255 3V 3.
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Downloaded from Arrow.com. Supply current in Shutdown mode (backup registers retained) RTC enabled IDD_ALL (Shutdown with RTC) Wakeup clock is MSI = 4 MHz. See (3). RTC clocked by LSE quartz (2) in low drive mode RTC clocked by LSE bypassed at 32768 Hz - Conditions 625 3.
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Electrical characteristics STM32L452xx I/O system current consumption The current consumption of the I/O system has two components: static and dynamic. I/O static current consumption All the I/Os used as inputs with pull-up generate current consumption when the pin is externally held low. The value of this current consumption can be simply computed by using the pull-up/pull-down resistors values given in Table 71: I/O static characteristics.
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STM32L452xx Electrical characteristics On-chip peripheral current consumption The current consumption of the on-chip peripherals is given in Table 51.
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Electrical characteristics STM32L452xx Table 51. Peripheral current consumption (continued) Range 1 Range 2 Low-power run and sleep RTCA 1.7 1.1 2.1 CRS 0.3 0.3 0.6 USB FS independent clock domain 2.9 N/A N/A USB FS clock domain 2.3 N/A N/A I2C1 independent clock domain 3.5 2.8 3.4 I2C1 clock domain 1.1 0.9 1.0 I2C2 independent clock domain 3.5 3.0 3.4 I2C2 clock domain 1.1 0.7 0.9 I2C3 independent clock domain 2.9 2.3 2.5 I2C3 clock domain 0.9 0.4 0.
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STM32L452xx Electrical characteristics Table 51. Peripheral current consumption (continued) Range 1 Range 2 Low-power run and sleep AHB to APB2(4) 1.0 0.9 0.9 FW 0.2 0.2 0.2 SAI1 independent clock domain 2.3 1.8 1.9 SAI1 clock domain 2.1 1.8 2.0 SDMMC1 independent clock domain 4.7 3.9 3.9 SDMMC1 clock domain 2.5 1.9 1.9 SPI1 1.8 1.6 1.7 SYSCFG/VREFBUF/COMP 0.6 0.5 0.6 TIM1 8.1 6.5 7.6 TIM15 3.7 3.0 3.4 TIM16 2.7 2.1 2.6 USART1 independent clock domain 4.8 4.
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Electrical characteristics STM32L452xx Table 52. Low-power mode wakeup timings(1) (continued) Symbol Parameter Conditions Range 1 Wake up time from Stop 0 mode to Run mode in Flash Range 2 tWUSTOP0 Range 1 Wake up time from Stop 0 mode to Run mode in SRAM1 Range 2 Range 1 Wake up time from Stop 1 mode to Run in Flash Range 1 tWUSTOP1 Wake up time from Stop 1 mode to Low-power run mode in Flash Wake up time from Stop 1 mode to Low-power run mode in SRAM1 122/210 Downloaded from Arrow.com.
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STM32L452xx Electrical characteristics Table 52. Low-power mode wakeup timings(1) (continued) Symbol Parameter Conditions Typ Max Wakeup clock MSI = 48 MHz 7.93 9.1 Wakeup clock HSI16 = 16 MHz 7.32 8.5 Wakeup clock MSI = 24 MHz 8.25 9.4 Wakeup clock HSI16 = 16 MHz 7.32 8.4 Wakeup clock MSI = 4 MHz 11.43 13.3 Wakeup clock MSI = 48 MHz 5.23 6 Wakeup clock HSI16 = 16 MHz 6.33 7.1 Wakeup clock MSI = 24 MHz 5.78 6.5 Wakeup clock HSI16 = 16 MHz 6.33 7.
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Electrical characteristics 6.3.7 STM32L452xx External clock source characteristics High-speed external user clock generated from an external source In bypass mode the HSE oscillator is switched off and the input pin is a standard GPIO. The external clock signal has to respect the I/O characteristics in Section 6.3.14. However, the recommended clock input waveform is shown in Figure 18: High-speed external clock source AC timing diagram. Table 55.
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STM32L452xx Electrical characteristics Low-speed external user clock generated from an external source In bypass mode the LSE oscillator is switched off and the input pin is a standard GPIO. The external clock signal has to respect the I/O characteristics in Section 6.3.14. However, the recommended clock input waveform is shown in Figure 19. Table 56.
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Electrical characteristics STM32L452xx High-speed external clock generated from a crystal/ceramic resonator The high-speed external (HSE) clock can be supplied with a 4 to 48 MHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on design simulation results obtained with typical external components specified in Table 57.
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STM32L452xx Note: Electrical characteristics For information on selecting the crystal, refer to the application note AN2867 “Oscillator design guide for ST microcontrollers” available from the ST website www.st.com. Figure 20. Typical application with an 8 MHz crystal 5HVRQDWRU ZLWK LQWHJUDWHG FDSDFLWRUV &/ 26&B,1 0+] UHVRQDWRU &/ 5(;7 I+6( 5) %LDV FRQWUROOHG JDLQ 26&B287 06 9 1. REXT value depends on the crystal characteristics.
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Electrical characteristics STM32L452xx 1. Guaranteed by design. 2. Refer to the note and caution paragraphs below the table, and to the application note AN2867 “Oscillator design guide for ST microcontrollers”. 3. tSU(LSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 kHz oscillation is reached.
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STM32L452xx 6.3.8 Electrical characteristics Internal clock source characteristics The parameters given in Table 59 are derived from tests performed under ambient temperature and supply voltage conditions summarized in Table 23: General operating conditions. The provided curves are characterization results, not tested in production. High-speed internal (HSI16) RC oscillator Table 59.
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Electrical characteristics STM32L452xx Figure 22. HSI16 frequency versus temperature 0+] PLQ PHDQ & PD[ 06Y 9 130/210 Downloaded from Arrow.com.
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STM32L452xx Electrical characteristics Multi-speed internal (MSI) RC oscillator Table 60. MSI oscillator characteristics(1) Symbol Parameter Conditions Min Typ Max Range 0 98.7 100 101.3 Range 1 197.4 200 202.6 Range 2 394.8 400 405.2 Range 3 789.6 800 810.4 Range 4 0.987 1 1.013 Range 5 1.974 2 2.026 Range 6 3.948 4 4.052 Range 7 7.896 8 8.104 Range 8 15.79 16 16.21 Range 9 23.69 24 24.31 Range 10 31.58 32 32.42 Range 11 47.38 48 48.62 Range 0 - 98.
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Electrical characteristics STM32L452xx Table 60. MSI oscillator characteristics(1) (continued) Symbol Parameter Conditions Min Typ VDD=1.62 V to 3.6 V -1.2 - VDD=2.4 V to 3.6 V -0.5 - VDD=1.62 V to 3.6 V -2.5 - VDD=2.4 V to 3.6 V -0.8 - VDD=1.62 V to 3.6 V -5 - VDD=2.4 V to 3.6 V -1.
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STM32L452xx Electrical characteristics Table 60. MSI oscillator characteristics(1) (continued) Symbol IDD(MSI)(6) Parameter MSI oscillator power consumption Conditions MSI and PLL mode Min Typ Max Range 0 - - 0.6 1 Range 1 - - 0.8 1.2 Range 2 - - 1.2 1.7 Range 3 - - 1.9 2.5 Range 4 - - 4.7 6 Range 5 - - 6.5 9 Range 6 - - 11 15 Range 7 - - 18.5 25 Range 8 - - 62 80 Range 9 - - 85 110 Range 10 - - 110 130 Range 11 - - 155 190 Unit µA 1.
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Electrical characteristics STM32L452xx Figure 23. Typical current consumption versus MSI frequency High-speed internal 48 MHz (HSI48) RC oscillator Table 61. HSI48 oscillator characteristics(1) Symbol Parameter fHSI48 HSI48 Frequency TRIM HSI48 user trimming step USER TRIM COVERAGE Conditions VDD=3.
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STM32L452xx Electrical characteristics Table 61. HSI48 oscillator characteristics(1) (continued) Symbol Parameter Conditions Min Typ Max Unit NT jitter Next transition jitter Accumulated jitter on 28 cycles(4) - - +/-0.15(2) - ns PT jitter Paired transition jitter Accumulated jitter on 56 cycles(4) - - +/-0.25(2) - ns 1. VDD = 3 V, TA = –40 to 125°C unless otherwise specified. 2. Guaranteed by design. 3. Guaranteed by characterization results. 4.
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Electrical characteristics 6.3.9 STM32L452xx PLL characteristics The parameters given in Table 63 are derived from tests performed under temperature and VDD supply voltage conditions summarized in Table 23: General operating conditions. Table 63. PLL, PLLSAI1 characteristics(1) Symbol fPLL_IN Parameter Conditions Min Typ Max Unit PLL input clock(2) - 4 - 16 MHz PLL input clock duty cycle - 45 - 55 % Voltage scaling Range 1 3.0968 - 80 Voltage scaling Range 2 3.
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STM32L452xx 6.3.10 Electrical characteristics Flash memory characteristics Table 64. Flash memory characteristics(1) Symbol Parameter Conditions Typ Max Unit tprog 64-bit programming time - 81.69 90.76 µs tprog_row one row (32 double word) programming time normal programming 2.61 2.90 fast programming 1.91 2.12 tprog_page one page (2 Kbyte) programming time normal programming 20.91 23.24 fast programming 15.29 16.98 22.02 24.47 normal programming 5.35 5.
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Electrical characteristics 6.3.11 STM32L452xx EMC characteristics Susceptibility tests are performed on a sample basis during device characterization. Functional EMS (electromagnetic susceptibility) While a simple application is executed on the device (toggling 2 LEDs through I/O ports). the device is stressed by two electromagnetic events until a failure occurs.
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STM32L452xx Electrical characteristics Prequalification trials Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1 second. To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015).
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Electrical characteristics STM32L452xx Static latch-up Two complementary static tests are required on six parts to assess the latch-up performance: • A supply overvoltage is applied to each power supply pin. • A current injection is applied to each input, output and configurable I/O pin. These tests are compliant with EIA/JESD 78A IC latch-up standard. Table 69. Electrical sensitivities Symbol LU 6.3.
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STM32L452xx 6.3.14 Electrical characteristics I/O port characteristics General input/output characteristics Unless otherwise specified, the parameters given in Table 71 are derived from tests performed under the conditions summarized in Table 23: General operating conditions. All I/Os are designed as CMOS- and TTL-compliant. Table 71. I/O static characteristics Symbol VIL(1) VIH(1) Vhys(3) Parameter Min Typ Max Unit I/O input low level voltage 1.62 V
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Electrical characteristics STM32L452xx Table 71. I/O static characteristics (continued) Symbol Parameter Conditions RPD Weak pull-down VIN = VDDIOx equivalent resistor(8) CIO I/O pin capacitance Min Typ Max Unit 25 40 55 kΩ - 5 - pF - 1. Refer to Figure 25: I/O input characteristics. 2. Tested in production. 3. Guaranteed by design. 4. Max(VDDXXX) is the maximum value of all the I/O supplies. Refer to Table: Legend/Abbreviations used in the pinout table. 5.
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STM32L452xx Electrical characteristics In the user application, the number of I/O pins which can drive current must be limited to respect the absolute maximum rating specified in Section 6.2: • The sum of the currents sourced by all the I/Os on VDDIOx, plus the maximum consumption of the MCU sourced on VDD, cannot exceed the absolute maximum rating ΣIVDD (see Table 20: Voltage characteristics).
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Electrical characteristics STM32L452xx Unless otherwise specified, the parameters given are derived from tests performed under the ambient temperature and supply voltage conditions summarized in Table 23: General operating conditions. Table 73. I/O AC characteristics(1)(2) Speed Symbol Fmax Parameter Maximum frequency 00 Tr/Tf Fmax Output rise and fall time Maximum frequency 01 Tr/Tf 144/210 Downloaded from Arrow.com. Output rise and fall time Conditions Min Max C=50 pF, 2.7 V≤VDDIOx≤3.
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STM32L452xx Electrical characteristics Table 73. I/O AC characteristics(1)(2) (continued) Speed Symbol Fmax Parameter Maximum frequency 10 Tr/Tf Fmax Output rise and fall time Maximum frequency 11 Tr/Tf Fm+ Fmax Tf Output rise and fall time Maximum frequency (4) Output fall time Conditions Min Max C=50 pF, 2.7 V≤VDDIOx≤3.6 V - 50 C=50 pF, 1.62 V≤VDDIOx≤2.7 V - 25 C=50 pF, 1.08 V≤VDDIOx≤1.62 V - 5 C=10 pF, 2.7 V≤VDDIOx≤3.6 V - 100(3) C=10 pF, 1.62 V≤VDDIOx≤2.7 V - 37.
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Electrical characteristics STM32L452xx Figure 26. I/O AC characteristics definition(1) W I ,2 RXW W U ,2 RXW 7 0D[LPXP IUHTXHQF\ LV DFKLHYHG LI W W U I 7 DQG LI WKH GXW\ F\FOH LV ZKHQ ORDGHG E\ WKH VSHFLILHG FDSDFLWDQFH 06 9 1. Refer to Table 73: I/O AC characteristics. 6.3.15 NRST pin characteristics The NRST pin input driver uses the CMOS technology. It is connected to a permanent pullup resistor, RPU.
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STM32L452xx Electrical characteristics Figure 27. Recommended NRST pin protection ([WHUQDO UHVHW FLUFXLW 9'' 1567 538 ,QWHUQDO UHVHW )LOWHU ) 06 9 1. The reset network protects the device against parasitic resets. 2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in Table 74: NRST pin characteristics. Otherwise the reset will not be taken into account by the device. 3.
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Electrical characteristics 6.3.17 STM32L452xx Analog-to-Digital converter characteristics Unless otherwise specified, the parameters given in Table 76 are preliminary values derived from tests performed under ambient temperature, fPCLK frequency and VDDA supply voltage conditions summarized in Table 23: General operating conditions. Note: It is recommended to perform a calibration after each power-up. Table 76.
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STM32L452xx Electrical characteristics Table 76. ADC characteristics(1) (2) (continued) Symbol Parameter tLATR Trigger conversion latency Regular and injected channels without conversion abort Conditions Min Typ Max CKMODE = 00 1.5 2 2.5 CKMODE = 01 - - 2.0 CKMODE = 10 - - 2.25 CKMODE = 11 - - 2.125 2.5 3 3.5 - - 3.0 - - 3.25 - - 3.125 0.03125 - 8.00625 µs - 2.5 - 640.5 1/fADC - - - 20 µs 0.1875 - 8.
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Electrical characteristics STM32L452xx Table 77. Maximum ADC RAIN(1)(2) Resolution 12 bits 10 bits 8 bits 6 bits Sampling cycle @80 MHz Sampling time [ns] @80 MHz 2.5 Fast channels(3) Slow channels(4) 31.25 100 N/A 6.5 81.25 330 100 12.5 156.25 680 470 24.5 306.25 1500 1200 47.5 593.75 2200 1800 92.5 1156.25 4700 3900 247.5 3093.75 12000 10000 640.5 8006.75 39000 33000 2.5 31.25 120 N/A 6.5 81.25 390 180 12.5 156.25 820 560 24.5 306.25 1500 1200 47.
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STM32L452xx Electrical characteristics 2. The I/O analog switch voltage booster is enable when VDDA < 2.4 V (BOOSTEN = 1 in the SYSCFG_CFGR1 when VDDA < 2.4V). It is disable when VDDA ≥ 2.4 V. 3. Fast channels are: PC0, PC1, PC2, PC3, PA0, PA1. 4. Slow channels are: all ADC inputs except the fast channels. DocID029968 Rev 3 151/210 186 Downloaded from Arrow.com.
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Electrical characteristics STM32L452xx Table 78. ADC accuracy - limited test conditions 1(1)(2)(3) Symbol Parameter ET Total unadjusted error EO Conditions(4) Single ended Differential Single ended Offset error Differential Single ended EG Gain error Differential ED EL Differential linearity ADC clock frequency ≤ error 80 MHz, Sampling rate ≤ 5.
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STM32L452xx Electrical characteristics Table 78. ADC accuracy - limited test conditions 1(1)(2)(3) (continued) Symbol THD Conditions(4) Parameter Total harmonic distortion ADC clock frequency ≤ Single 80 MHz, ended Sampling rate ≤ 5.33 Msps, VDDA = VREF+ = 3 V, Differential TA = 25 °C Min Typ Max Unit Fast channel (max speed) - -74 -73 Slow channel (max speed) - -74 -73 Fast channel (max speed) - -79 -76 Slow channel (max speed) - -79 -76 dB 1. Guaranteed by design. 2.
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Electrical characteristics STM32L452xx Table 79. ADC accuracy - limited test conditions 2(1)(2)(3) Symbol Parameter ET Total unadjusted error EO Conditions(4) Single ended Differential Single ended Offset error Differential Single ended EG Gain error Differential ED EL Differential linearity error ADC clock frequency ≤ 80 MHz, Sampling rate ≤ 5.
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STM32L452xx Electrical characteristics Table 79. ADC accuracy - limited test conditions 2(1)(2)(3) (continued) Symbol THD Conditions(4) Parameter Total harmonic distortion Fast channel (max speed) Single ADC clock frequency ≤ ended Slow channel (max speed) 80 MHz, Sampling rate ≤ 5.33 Msps, Fast channel (max speed) Differential 2 V ≤ VDDA Slow channel (max speed) Min Typ Max Unit - -74 -65 - -74 -67 - -79 -70 - -79 -71 dB 1. Guaranteed by design. 2.
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Electrical characteristics STM32L452xx Table 80. ADC accuracy - limited test conditions 3(1)(2)(3) Symbol Parameter ET Total unadjusted error EO Conditions(4) Single ended Differential Single ended Offset error Differential Single ended EG Gain error Differential ED EL Differential linearity ADC clock frequency ≤ error 80 MHz, Sampling rate ≤ 5.33 Msps, 1.65 V ≤ VDDA = VREF+ ≤ 3.
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STM32L452xx Electrical characteristics Table 80. ADC accuracy - limited test conditions 3(1)(2)(3) (continued) Symbol THD Conditions(4) Parameter Total harmonic distortion ADC clock frequency ≤ Single 80 MHz, ended Sampling rate ≤ 5.33 Msps, 1.65 V ≤ VDDA = VREF+ ≤ Differential 3.6 V, Voltage scaling Range 1 Min Typ Max Unit Fast channel (max speed) - -69 -67 Slow channel (max speed) - -71 -67 Fast channel (max speed) - -72 -71 Slow channel (max speed) - -72 -71 dB 1.
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Electrical characteristics STM32L452xx Table 81. ADC accuracy - limited test conditions 4(1)(2)(3) Symbol Parameter ET Total unadjusted error EO Conditions(4) Single ended Differential Single ended Offset error Differential Single ended EG Gain error Differential ED EL Differential linearity ADC clock frequency ≤ error 26 MHz, 1.65 V ≤ VDDA = VREF+ ≤ 3.
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STM32L452xx Electrical characteristics Table 81. ADC accuracy - limited test conditions 4(1)(2)(3) (continued) Symbol THD Conditions(4) Parameter ADC clock frequency ≤ 26 MHz, 1.65 V ≤ VDDA = VREF+ ≤ 3.6 V, Voltage scaling Range 2 Total harmonic distortion Single ended Differential Min Typ Max Unit Fast channel (max speed) - -71 -69 Slow channel (max speed) - -71 -69 Fast channel (max speed) - -73 -72 Slow channel (max speed) - -73 -72 dB 1. Guaranteed by design. 2.
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Electrical characteristics STM32L452xx Figure 29. Typical connection diagram using the ADC 9''$ 97 5$,1 9$,1 6DPSOH DQG KROG $'& FRQYHUWHU 5$'& $,1[ &SDUDVLWLF 97 ,ONJ ELW FRQYHUWHU &$'& 06 9 1. Refer to Table 76: ADC characteristics for the values of RAIN and CADC. 2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad capacitance (refer to Table 71: I/O static characteristics for the value of the pad capacitance).
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STM32L452xx 6.3.18 Electrical characteristics Digital-to-Analog converter characteristics Table 82. DAC characteristics(1) Symbol VDDA VREF+ VREF- Parameter Analog supply voltage for DAC ON Positive reference voltage Conditions Min Typ DAC output buffer OFF, DAC_OUT pin not connected (internal connection only) 1.71 - Other modes 1.80 - DAC output buffer OFF, DAC_OUT pin not connected (internal connection only) 1.71 - Other modes 1.80 Negative reference voltage Max 3.
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Electrical characteristics STM32L452xx Table 82. DAC characteristics(1) (continued) Symbol TW_to_W tSAMP Parameter Conditions Typ Max Unit - - µs - 0.7 3.5 - 10.5 18 - 2 3.5 µs - - -(3) nA 5.2 7 8.8 pF 50 - - µs VREF+ = 3.6 V - 1500 - VREF+ = 1.8 V - 750 - No load, middle code (0x800) - 315 500 No load, worst code (0xF1C) - 450 670 No load, middle code (0x800) - - 0.
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STM32L452xx Electrical characteristics Table 82.
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Electrical characteristics STM32L452xx Table 83. DAC accuracy(1) . Symbol Parameter DNL Differential non linearity (2) - monotonicity 10 bits INL Integral non linearity(3) Offset Offset1 OffsetCal Gain TUE TUECal SNR THD 164/210 Downloaded from Arrow.com.
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STM32L452xx Electrical characteristics Table 83. DAC accuracy(1) (continued) Symbol Parameter SINAD Signal-to-noise and distortion ratio ENOB Effective number of bits Conditions Min Typ Max DAC output buffer ON CL ≤ 50 pF, RL ≥ 5 kΩ, 1 kHz - 70.4 - DAC output buffer OFF CL ≤ 50 pF, no RL, 1 kHz - 71 - DAC output buffer ON CL ≤ 50 pF, RL ≥ 5 kΩ, 1 kHz - 11.4 - DAC output buffer OFF CL ≤ 50 pF, no RL, 1 kHz - Unit dB bits 11.5 - 1. Guaranteed by design. 2.
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Electrical characteristics 6.3.19 STM32L452xx Voltage reference buffer characteristics Table 84. VREFBUF characteristics(1) Symbol Parameter Conditions Normal mode VDDA VREFBUF_ OUT Analog supply voltage Voltage reference output Degraded mode(2) Normal mode Degraded mode(2) Min Typ Max VRS = 0 2.4 - 3.6 VRS = 1 2.8 - 3.6 VRS = 0 1.65 - 2.4 VRS = 1 1.65 - 2.8 2.048 2.049(3) (3) VRS = 0 2.046 VRS = 1 2.498(3) 2.5 2.
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STM32L452xx Electrical characteristics Table 84. VREFBUF characteristics(1) (continued) Symbol Parameter VREFBUF IDDA(VREF consumption BUF) from VDDA Conditions Min Typ Max Iload = 0 µA - 16 25 Iload = 500 µA - 18 30 Iload = 4 mA - 35 50 Unit µA 1. Guaranteed by design, unless otherwise specified. 2. In degraded mode, the voltage reference buffer can not maintain accurately the output voltage which will follow (VDDA drop voltage). 3. Guaranteed by test in production. 4.
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Electrical characteristics 6.3.20 STM32L452xx Comparator characteristics Table 85. COMP characteristics(1) Symbol Conditions Min Typ Max Analog supply voltage - 1.62 - 3.6 Comparator input voltage range - 0 - VDDA V VBG(2) Scaler input voltage - VSC Scaler offset voltage - VDDA VIN IDDA(SCALER) Parameter VREFINT - ±5 ±10 mV BRG_EN=0 (bridge disable) - 200 300 nA BRG_EN=1 (bridge enable) - 0.8 1 µA - 100 200 µs VDDA ≥ 2.7 V - - 5 VDDA < 2.
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STM32L452xx Electrical characteristics Table 85.
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Electrical characteristics STM32L452xx Table 86.
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STM32L452xx Electrical characteristics Table 86.
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Electrical characteristics STM32L452xx Table 86.
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STM32L452xx 6.3.23 Electrical characteristics VBAT monitoring characteristics Table 88. VBAT monitoring characteristics Symbol Parameter Min Typ Max Unit R Resistor bridge for VBAT - 39 - kΩ Q Ratio on VBAT measurement - 3 - - Error on Q -10 - 10 % ADC sampling time when reading the VBAT 12 - - µs Er (1) (1) tS_vbat 1. Guaranteed by design. Table 89. VBAT charging characteristics Symbol RBC 6.3.
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Electrical characteristics STM32L452xx Table 91. IWDG min/max timeout period at 32 kHz (LSI)(1) Prescaler divider PR[2:0] bits Min timeout RL[11:0]= 0x000 Max timeout RL[11:0]= 0xFFF /4 0 0.125 512 /8 1 0.250 1024 /16 2 0.500 2048 /32 3 1.0 4096 /64 4 2.0 8192 /128 5 4.0 16384 /256 6 or 7 8.0 32768 Unit ms 1. The exact timings still depend on the phasing of the APB interface clock versus the LSI clock so that there is always a full RC period of uncertainty. Table 92.
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STM32L452xx Electrical characteristics Table 93. I2C analog filter characteristics(1) Symbol Parameter Min Max Unit tAF Maximum pulse width of spikes that are suppressed by the analog filter 50(2) 260(3) ns 1. Guaranteed by design. 2. Spikes with widths below tAF(min) are filtered. 3. Spikes with widths above tAF(max) are not filtered DocID029968 Rev 3 175/210 186 Downloaded from Arrow.com.
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Electrical characteristics STM32L452xx SPI characteristics Unless otherwise specified, the parameters given in Table 94 for SPI are derived from tests performed under the ambient temperature, fPCLKx frequency and supply voltage conditions summarized in Table 23: General operating conditions. • Output speed is set to OSPEEDRy[1:0] = 11 • Capacitive load C = 30 pF • Measurement points are done at CMOS levels: 0.5 ₓ VDD Refer to Section 6.3.
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STM32L452xx Electrical characteristics Table 94. SPI characteristics(1) (continued) Symbol tv(SO) Parameter Data output valid time tv(MO) th(SO) Data output hold time th(MO) Conditions Min Typ Max Slave mode 2.7 < VDD < 3.6 V Voltage Range 1 - 12.5 13.5 Slave mode 1.71 < VDD < 3.6 V Voltage Range 1 - 12.5 24 Slave mode 1.71 < VDD < 3.6 V Voltage Range 2 - 12.5 33 Master mode - 4.5 6 Slave mode 7 - - Master mode 0 - - Unit ns ns 1.
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Electrical characteristics STM32L452xx Figure 32. SPI timing diagram - slave mode and CPHA = 1 166 LQSXW WF 6&. WVX 166 WZ 6&.+ WD 62 WZ 6&./ WI 6&. WK 166 6&. LQSXW &3+$ &32/ &3+$ &32/ 0,62 RXWSXW WY 62 WK 62 )LUVW ELW 287 WVX 6, 1H[W ELWV 287 WU 6&. WGLV 62 /DVW ELW 287 WK 6, 026, LQSXW )LUVW ELW ,1 1H[W ELWV ,1 /DVW ELW ,1 06Y 9 1. Measurement points are done at CMOS levels: 0.3 VDD and 0.7 VDD. Figure 33. SPI timing diagram - master mode +LJK 166 LQSXW 6&.
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STM32L452xx Electrical characteristics Quad SPI characteristics Unless otherwise specified, the parameters given in Table 95 and Table 96 for Quad SPI are derived from tests performed under the ambient temperature, fAHB frequency and VDD supply voltage conditions summarized in Table 23: General operating conditions, with the following configuration: • Output speed is set to OSPEEDRy[1:0] = 11 • Capacitive load C = 15 or 20 pF • Measurement points are done at CMOS levels: 0.5 ₓ VDD Refer to Section 6.3.
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Electrical characteristics STM32L452xx Table 96. QUADSPI characteristics in DDR mode(1) Symbol FCK 1/t(CK) tw(CKH) tw(CKL) Parameter Quad SPI clock frequency Quad SPI clock high and low time Conditions Min Typ Max 1.71 < VDD < 3.6 V, CLOAD = 20 pF Voltage Range 1 - - 40 2 < VDD < 3.6 V, CLOAD = 20 pF Voltage Range 1 - - 48 1.71 < VDD < 3.6 V, CLOAD = 15 pF Voltage Range 1 - - 48 1.71 < VDD < 3.
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STM32L452xx Electrical characteristics Figure 34. Quad SPI timing diagram - SDR mode WU &. &ORFN W &. WZ &.+ WY 287 WZ &./ WI &. WK 287 'DWD RXWSXW ' ' WV ,1 'DWD LQSXW ' WK ,1 ' ' ' 06Y 9 Figure 35. Quad SPI timing diagram - DDR mode WU &. &ORFN 'DWD RXWSXW W &. WYI 287 WZ &.+ WKU 287 ' WYU 287 ' ' WZ &./ WKI 287 ' WVI ,1 WKI ,1 'DWD LQSXW ' ' WI &. ' ' WVU ,1 WKU ,1 ' ' ' ' 06Y 9 DocID029968 Rev 3 181/210 186 Downloaded from Arrow.com.
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Electrical characteristics STM32L452xx SAI characteristics Unless otherwise specified, the parameters given in Table 97 for SAI are derived from tests performed under the ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized inTable 23: General operating conditions, with the following configuration: • Output speed is set to OSPEEDRy[1:0] = 10 • Capacitive load C = 30 pF • Measurement points are done at CMOS levels: 0.5 ₓ VDD Refer to Section 6.3.
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STM32L452xx Electrical characteristics Table 97. SAI characteristics(1) (continued) Symbol tv(SD_B_ST) th(SD_B_ST) tv(SD_A_MT) th(SD_A_MT) Parameter Conditions Data output valid time Data output hold time Data output valid time Data output hold time Min Max Slave transmitter (after enable edge) 2.7 ≤ VDD ≤ 3.6 - 22 Slave transmitter (after enable edge) 1.71 ≤ VDD ≤ 3.6 - 34 Slave transmitter (after enable edge) 10 - Master transmitter (after enable edge) 2.7 ≤ VDD ≤ 3.
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Electrical characteristics STM32L452xx Figure 37.
PAGE 185
STM32L452xx Electrical characteristics Table 98. SD / MMC dynamic characteristics, VDD=2.7 V to 3.6 V(1) (continued) Symbol Parameter Conditions Min Typ Max Unit CMD, D outputs (referenced to CK) in SD default mode tOVD Output valid default time SD fPP = 50 MHz - 2 3 ns tOHD Output hold default time SD fPP = 50 MHz 0 - - ns 1. Guaranteed by characterization results. Table 99. eMMC dynamic characteristics, VDD = 1.71 V to 1.
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Electrical characteristics STM32L452xx Figure 39. SD default mode #+ T/6$ T/($ $ #-$ OUTPUT AI USB characteristics The STM32L452xx USB interface is fully compliant with the USB specification version 2.0 and is USB-IF certified (for Full-speed device operation). Table 100. USB electrical characteristics(1) Symbol Min Typ Max Unit 3.0(2) - 3.
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STM32L452xx 7 Package information Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. 7.1 LQFP100 package information Figure 40. LQFP100 - 100-pin, 14 x 14 mm low-profile quad flat package outline MM C ! ! ! 3%!4).' 0,!.% # '!5'% 0,!.
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Package information STM32L452xx Table 101. LQPF100 - 100-pin, 14 x 14 mm low-profile quad flat package mechanical data (continued) inches(1) millimeters Symbol Min Typ Max Min Typ Max A2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 D 15.800 16.000 16.200 0.6220 0.6299 0.6378 D1 13.800 14.000 14.200 0.5433 0.5512 0.5591 D3 - 12.000 - - 0.4724 - E 15.800 16.000 16.200 0.6220 0.6299 0.
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STM32L452xx Package information Device marking The following figure gives an example of topside marking orientation versus pin 1 identifier location. Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. Figure 42. LQFP100 marking (package top view) 3URGXFW LGHQWLILFDWLRQ 670 / 2SWLRQDO JDWH PDUN 9(7 % 5HYLVLRQ FRGH 'DWH FRGH < :: 3LQ LQGHQWLILHU 06Y 9 1.
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Package information 7.2 STM32L452xx UFBGA100 package information Figure 43. UFBGA100 - 100-ball, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array package outline = 6HDWLQJ SODQH GGG = $ $ $ $ $ ( $ EDOO $ EDOO LGHQWLILHU LQGH[ DUHD = H ; ( $ = ' ' H < 0 %27720 9,(: E EDOOV HHH 0 = < ; III 0 = 723 9,(: $ & B0(B9 1. Drawing is not to scale. Table 102. UFBGA100 - 100-ball, 7 x 7 mm, 0.
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STM32L452xx Package information Table 102. UFBGA100 - 100-ball, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array package mechanical data (continued) inches(1) millimeters Symbol Min. Typ. Max. Min. Typ. Max. Z - 0.750 - - 0.0295 - ddd - - 0.080 - - 0.0031 eee - - 0.150 - - 0.0059 fff - - 0.050 - - 0.0020 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 44. UFBGA100 - 100-ball, 7 x 7 mm, 0.
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Package information STM32L452xx Figure 45. UFBGA100 marking (package top view) 3URGXFW LGHQWLILFDWLRQ 670 / 9(, < :: 'DWH FRGH % 3LQ LGHQWLILHU 06Y 9 1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering samples in production.
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STM32L452xx 7.3 Package information LQFP64 package information Figure 46. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package outline PP *$8*( 3/$1( F $ $ $ 6($7,1* 3/$1( & $ FFF & ' ' ' . / / 3,1 ,'(17,),&$7,21 ( ( ( E H :B0(B9 1. Drawing is not to scale. Table 104. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A - - 1.600 - - 0.0630 A1 0.
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Package information STM32L452xx Table 104. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package mechanical data (continued) inches(1) millimeters Symbol Min Typ Max Min Typ Max E3 - 7.500 - - 0.2953 - e - 0.500 - - 0.0197 - K 0° 3.5° 7° 0° 3.5° 7° L 0.450 0.600 0.750 0.0177 0.0236 0.0295 L1 - 1.000 - - 0.0394 - ccc - - 0.080 - - 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 47.
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STM32L452xx Package information Figure 48. LQFP64 marking (package top view) 5HYLVLRQ FRGH % 3URGXFW LGHQWLILFDWLRQ 670 / 5(7 < :: 'DWH FRGH 3LQ LGHQWLILHU 06Y 9 1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge.
PAGE 196
Package information 7.4 STM32L452xx UFBGA64 package information Figure 49. UFBGA64 – 64-ball, 5 x 5 mm, 0.5 mm pitch ultra profile fine pitch ball grid array package outline = 6HDWLQJ SODQH GGG = $ $ $ $ $ ( H ; $ EDOO $ EDOO LGHQWLILHU LQGH[ DUHD ) ( $ ) ' ' H < + E EDOOV HHH 0 = < ; III 0 = %27720 9,(: 723 9,(: $ B0(B9 1. Drawing is not to scale. Table 105. UFBGA64 – 64-ball, 5 x 5 mm, 0.
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STM32L452xx Package information Table 105. UFBGA64 – 64-ball, 5 x 5 mm, 0.5 mm pitch ultra profile fine pitch ball grid array package mechanical data (continued) inches(1) millimeters Symbol Min Typ Max Min Typ Max A 0.460 0.530 0.600 0.0181 0.0209 0.0236 F 0.700 0.750 0.800 0.0276 0.0295 0.0315 ddd - - 0.080 - - 0.0031 eee - - 0.150 - - 0.0059 fff - - 0.050 - - 0.0020 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 50.
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Package information STM32L452xx Figure 51. UFBGA64 marking (package top view) 3URGXFW LGHQWLILFDWLRQ / 5(, < :: 'DWH FRGH % 3LQ LGHQWLILHU 06Y 9 1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering samples in production.
PAGE 199
STM32L452xx 7.5 Package information WLCSP64 package information Figure 52. WLCSP64 - 64-ball, 3.357x3.657 mm 0.4 mm pitch wafer level chip scale package outline 25,(17$7,21 5()(5(1&( ) H * '(7$,/ $ $ H ( ( H H $ ' ' %27720 9,(: %803 6,'( $ 723 9,(: :$)(5 %$&. 6,'( $ 6,'( 9,(: $ %803 )5217 9,(: $ E '(7$,/ $ 527$7(' $ 3B0(B9 1. Dimensions are expressed in millimeters. DocID029968 Rev 3 199/10 207 Downloaded from Arrow.com.
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Package information STM32L452xx Table 107. WLCSP64 - 64-ball, 3.357x3.657 mm 0.4 mm pitch wafer level chip scale mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A 0.525 0.555 0.585 0.0207 0.0219 0.0230 A1 - 0.175 - - 0.0069 - A2 - 0.380 - - 0.0150 - A3 - 0.025 - - 0.0010 - b 0.220 0.250 0.280 0.0087 0.0098 0.0110 D 3.322 3.357 3.392 0.1308 0.1322 0.1335 E 3.622 3.657 3.692 0.1426 0.1440 0.1454 e - 0.400 - - 0.
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STM32L452xx Package information Table 108. WLCSP64 recommended PCB design rules (0.4 mm pitch) Dimension Recommended values Pitch 0.4 mm Dpad 0.225 mm Dsm 0.290 mm typ. (depends on the soldermask registration tolerance) Stencil opening 0.250 mm Stencil thickness 0.100 mm Device marking The following figure gives an example of topside marking orientation versus ball A1 identifier location.
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Package information 7.6 STM32L452xx UFQFPN48 package information Figure 55. UFQFPN48 - 48-lead, 7x7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat package outline 3LQ LGHQWLILHU ODVHU PDUNLQJ DUHD ' $ ( ( 7 GGG $ 6HDWLQJ SODQH E H 'HWDLO < ' ([SRVHG SDG DUHD < ' / & [ SLQ FRUQHU ( 5 W\S 'HWDLO = = $ % B0(B9 1. Drawing is not to scale. 2. All leads/pads should also be soldered to the PCB to improve the lead/pad solder joint life. 3.
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STM32L452xx Package information Table 109. UFQFPN48 - 48-lead, 7x7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A 0.500 0.550 0.600 0.0197 0.0217 0.0236 A1 0.000 0.020 0.050 0.0000 0.0008 0.0020 D 6.900 7.000 7.100 0.2717 0.2756 0.2795 E 6.900 7.000 7.100 0.2717 0.2756 0.2795 D2 5.500 5.600 5.700 0.2165 0.2205 0.2244 E2 5.500 5.600 5.700 0.2165 0.2205 0.2244 L 0.300 0.
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Package information STM32L452xx Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. Figure 57. UFQFPN48 marking (package top view) 670 / 3URGXFW LGHQWLILFDWLRQ &(8 < :: 3LQ LGHQWLILHU 'DWH FRGH % 5HYLVLRQ FRGH 06Y 9 1.
PAGE 205
STM32L452xx 7.7 Package information Thermal characteristics The maximum chip-junction temperature, TJ max, in degrees Celsius, may be calculated using the following equation: TJ max = TA max + (PD max x ΘJA) Where: • TA max is the maximum ambient temperature in °C, • ΘJA is the package junction-to-ambient thermal resistance, in °C/W, • PD max is the sum of PINT max and PI/O max (PD max = PINT max + PI/Omax), • PINT max is the product of all IDDXXX and VDDXXX, expressed in Watts.
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Package information STM32L452xx The following examples show how to calculate the temperature range needed for a given application. Example 1: High-performance application Assuming the following application conditions: Maximum ambient temperature TAmax = 75 °C (measured according to JESD51-2), IDDmax = 50 mA, VDD = 3.5 V, maximum 20 I/Os used at the same time in output at low level with IOL = 8 mA, VOL= 0.4 V and maximum 8 I/Os used at the same time in output at low level with IOL = 20 mA, VOL= 1.
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STM32L452xx Package information In this case, parts must be ordered at least with the temperature range suffix 3 (see Section 8: Part numbering) unless we reduce the power dissipation in order to be able to use suffix 6 parts. Refer to Figure 58 to select the required temperature range (suffix 6 or 3) according to your ambient temperature or power requirements. Figure 58. LQFP64 PD max vs.
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Part numbering 8 STM32L452xx Part numbering Table 111.
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STM32L452xx 9 Revision history Revision history Table 112. Document revision history Date Revision 04-Apr-2017 1 Initial release. 2 Removed Suffix 7 ordering code and all information related to 40-105 °C temperature range. Updated ULPBench® score on cover page. Updated some power consumptions on cover page. Updated Table 2: STM32L452xx family device features and peripheral counts.
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