Datasheet
Electrical characteristics STM32L433xx
180/224 DocID028794 Rev 4
6.3.25 Timer characteristics
The parameters given in the following tables are guaranteed by design.
Refer to Section 6.3.14: I/O port characteristics for details on the input/output alternate
function characteristics (output compare, input capture, external clock, PWM output).
1. Guaranteed by design.
2. LCD enabled with 3 V internal step-up active, 1/8 duty, 1/4 bias, division ratio= 64, all pixels active, no LCD connected.
Table 90. TIMx
(1)
characteristics
1. TIMx
,
is used as a general term in which x stands for 1,2,3,4,5,6,7,8,15,16 or 17.
Symbol Parameter Conditions Min Max Unit
t
res(TIM)
Timer resolution time
-1-t
TIMxCLK
f
TIMxCLK
= 80 MHz 12.5 - ns
f
EXT
Timer external clock
frequency on CH1 to CH4
-0f
TIMxCLK
/2 MHz
f
TIMxCLK
= 80 MHz 0 40 MHz
Res
TIM
Timer resolution
TIMx (except
TIM2)
-16
bit
TIM2 - 32
t
COUNTER
16-bit counter clock
period
- 1 65536 t
TIMxCLK
f
TIMxCLK
= 80 MHz 0.0125 819.2 µs
t
MAX_COUNT
Maximum possible count
with 32-bit counter
- - 65536 × 65536 t
TIMxCLK
f
TIMxCLK
= 80 MHz - 53.68 s
Table 91. IWDG min/max timeout period at 32 kHz (LSI)
(1)
1. The exact timings still depend on the phasing of the APB interface clock versus the LSI clock so that there
is always a full RC period of uncertainty.
Prescaler divider PR[2:0] bits
Min timeout RL[11:0]=
0x000
Max timeout RL[11:0]=
0xFFF
Unit
/4 0 0.125 512
ms
/8 1 0.250 1024
/16 2 0.500 2048
/32 3 1.0 4096
/64 4 2.0 8192
/128 5 4.0 16384
/256 6 or 7 8.0 32768
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