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This is information on a product in full production.

June 2017 DocID028794 Rev 4 1/224

STM32L433xx

Ultra-low-power ARM

Cortex

-M4 32-bit MCU+FPU, 100DMIPS,

up to 256KB Flash, 64KB SRAM, USB FS, LCD, ext. SMPS

Datasheet - production data

Features

• Ultra-low-power with FlexPowerControl

– 1.71 V to 3.6 V power supply

– -40 °C to 85/105/125 °C temperature range

– 200 nA in V

BAT

mode: supply for RTC and

32x32-bit backup registers

– 8 nA Shutdown mode (5 wakeup pins)

– 28 nA Standby mode (5 wakeup pins)

– 280 nA Standby mode with RTC

– 1.0 µA Stop 2 mode, 1.28 µA with RTC

– 84 µA/MHz run mode (LDO Mode)

–36 A/MHz run mode (@3.3 V SMPS

Mode)

– Batch acquisition mode (BAM)

– 4 µs wakeup from Stop mode

– Brown out reset (BOR)

– Interconnect matrix

• Core: ARM

32-bit Cortex

-M4 CPU with FPU,

Adaptive real-time accelerator (ART

Accelerator™) allowing 0-wait-state execution

from Flash memory, frequency up to 80 MHz,

MPU, 100DMIPS and DSP instructions

• Performance benchmark

– 1.25 DMIPS/MHz (Drystone 2.1)

– 273.55 CoreMark

(3.42 CoreMark/MHz @

80 MHz)

• Energy benchmark

– 253 ULPBench

score

• Clock Sources

– 4 to 48 MHz crystal oscillator

– 32 kHz crystal oscillator for RTC (LSE)

– Internal 16 MHz factory-trimmed RC (±1%)

– Internal low-power 32 kHz RC (±5%)

– Internal multispeed 100 kHz to 48 MHz

oscillator, auto-trimmed by LSE (better than

±0.25 % accuracy)

– Internal 48 MHz with clock recovery

– 2 PLLs for system clock, USB, audio, ADC

• Up to 83 fast I/Os, most 5 V-tolerant

• RTC with HW calendar, alarms and calibration

• LCD 8× 40 or 4× 44 with step-up converter

• Up to 21 capacitive sensing channels: support

touchkey, linear and rotary touch sensors

• 11x timers: 1x 16-bit advanced motor-control,

1x 32-bit and 2x 16-bit general purpose, 2x 16-

bit basic, 2x low-power 16-bit timers (available

in Stop mode), 2x watchdogs, SysTick timer

• Memories

– Up to 256 KB single bank Flash,

proprietary code readout protection

– 64 KB of SRAM including 16 KB with

hardware parity check

– Quad SPI memory interface

• Rich analog peripherals (independent supply)

– 1× 12-bit ADC 5 Msps, up to 16-bit with

hardware oversampling, 200 µA/Msps

– 2x 12-bit DAC, low-power sample and hold

– 1x operational amplifier with built-in PGA

– 2x ultra-low-power comparators

• 17x communication interfaces

– USB 2.0 full-speed crystal less solution

with LPM and BCD

– 1x SAI (serial audio interface)

–3x I2C FM+(1 Mbit/s), SMBus/PMBus

– 4x USARTs (ISO 7816, LIN, IrDA, modem)

– 1x LPUART (Stop2 wake-up)

– 3x SPIs (4x SPIs with the Quad SPI)

– CAN (2.0B Active) and SDMMC interface

– SWPMI single wire protocol master I/F

– IRTIM (Infrared interface)

• 14-channel DMA controller

UFBGA100 (7

LQFP64 (10x10)

UFBGA64 (5x5)

LQFP48 (7x7)

LQFP100 (14x14)

WLCSP64

UFQFPN48 (7x7)

WLCSP49

www.st.com

Downloaded from Arrow.com.

Summary of content (224 pages)

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STM32L433xx Ultra-low-power ARM® Cortex®-M4 32-bit MCU+FPU, 100DMIPS, up to 256KB Flash, 64KB SRAM, USB FS, LCD, ext. SMPS Datasheet - production data Features • Ultra-low-power with FlexPowerControl – 1.71 V to 3.6 V power supply – -40 °C to 85/105/125 °C temperature range – 200 nA in VBAT mode: supply for RTC and 32x32-bit backup registers – 8 nA Shutdown mode (5 wakeup pins) – 28 nA Standby mode (5 wakeup pins) – 280 nA Standby mode with RTC – 1.0 µA Stop 2 mode, 1.
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STM32L433xx • True random number generator • Development support: serial wire debug (SWD), JTAG, Embedded Trace Macrocell™ • CRC calculation unit, 96-bit unique ID Table 1. Device summary Reference STM32L433xx 2/224 Downloaded from Arrow.com.
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STM32L433xx Contents Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.1 ARM® Cortex®-M4 core with FPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.
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Contents STM32L433xx 3.17 Voltage reference buffer (VREFBUF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3.18 Comparators (COMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.19 Operational amplifier (OPAMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.20 Touch sensing controller (TSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.21 Liquid crystal display controller (LCD) . . . . . . . . . . . . .
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STM32L433xx 6 Contents Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 6.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 6.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 6.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 6.1.3 Typical curves . . . . . . . . . . . . . . . . . . . .
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Contents STM32L433xx 6.3.26 7 Communication interfaces characteristics . . . . . . . . . . . . . . . . . . . . . . 181 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 7.1 LQFP100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 7.2 UFBGA100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 7.3 LQFP64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . .
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STM32L433xx List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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List of tables Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45. Table 46. Table 47. Table 48. Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. Table 62. Table 63. Table 64. Table 65. Table 66. Table 67. Table 68. Table 69. Table 70. Table 71. Table 72. Table 73. Table 74. Table 75. Table 76. Table 77. Table 78. Table 79. Table 80. Table 81. 8/224 Downloaded from Arrow.com.
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STM32L433xx Table 82. Table 83. Table 84. Table 85. Table 86. Table 87. Table 88. Table 89. Table 90. Table 91. Table 92. Table 93. Table 94. Table 95. Table 96. Table 97. Table 98. Table 99. Table 100. Table 101. Table 102. Table 103. Table 104. Table 105. Table 106. Table 107. Table 108. Table 109. Table 110. Table 111. Table 112. Table 113. Table 114. Table 115. Table 116. List of tables DAC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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List of figures STM32L433xx List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42. Figure 43.
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STM32L433xx Figure 46. Figure 47. Figure 48. Figure 49. Figure 50. Figure 51. Figure 52. Figure 53. Figure 54. Figure 55. Figure 56. Figure 57. Figure 58. Figure 59. Figure 60. Figure 61. Figure 62. Figure 63. Figure 64. Figure 65. Figure 66. List of figures UFBGA100 - 100-ball, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 UFBGA100 marking (package top view) . . . . . . . . . . . .
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Introduction 1 STM32L433xx Introduction This datasheet provides the ordering information and mechanical device characteristics of the STM32L433xx microcontrollers. This document should be read in conjunction with the STM32L43xxx/44xxx/45xxx/46xxx reference manual (RM0394). The reference manual is available from the STMicroelectronics website www.st.com. For information on the ARM® Cortex®-M4 core, please refer to the Cortex®-M4 Technical Reference Manual, available from the www.arm.com website.
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STM32L433xx 2 Description Description The STM32L433xx devices are the ultra-low-power microcontrollers based on the highperformance ARM® Cortex®-M4 32-bit RISC core operating at a frequency of up to 80 MHz. The Cortex-M4 core features a Floating point unit (FPU) single precision which supports all ARM single-precision data-processing instructions and data types. It also implements a full set of DSP instructions and a memory protection unit (MPU) which enhances application security.
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Description STM32L433xx Table 2. STM32L433xx family device features and peripheral counts Peripheral Flash memory STM32L433Vx 256KB STM32L433Rx 128KB 256KB SRAM Timers 256KB Yes Advanced control 1 (16-bit) General purpose 2 (16-bit) 1 (32-bit) Basic 2 (16-bit) Low -power 2 (16-bit) SysTick timer 1 Watchdog timers (independent, window) 2 SPI 3 I2C 3 USART LPUART 3 1 Comm.
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STM32L433xx Description Table 2. STM32L433xx family device features and peripheral counts (continued) Peripheral STM32L433Vx STM32L433Rx Operational amplifiers 1 Max. CPU frequency 80 MHz Operating voltage (VDD) 1.71 to 3.6 V Operating voltage (VDD12) 1.05 to 1.32 V Ambient operating temperature: -40 to 85 °C / -40 to 105 °C / -40 to 125 °C Junction temperature: -40 to 105 °C / -40 to 125 °C / -40 to 130 °C Operating temperature Packages 1.
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Description STM32L433xx Figure 1. STM32L433xx block diagram ' > @ ' > @ &/. &/. &6 1-7567 -7', -7&. 6:&/. 4XDG 63, PHPRU\ LQWHUIDFH -7$* 6: 038 (70 19,& -7'2 6:' -7'2 75$&(&/. ' %86 75$&('> @ $50 &RUWH[ 0 0+] )38 , %86 $57 $&&(/ &$&+( 51* )ODVK XS WR .% $+% EXV PDWUL[ 6 %86 65$0 .% 65$0 .
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STM32L433xx Functional overview 3 Functional overview 3.1 ARM® Cortex®-M4 core with FPU The ARM® Cortex®-M4 with FPU processor is the latest generation of ARM processors for embedded systems. It was developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced response to interrupts.
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Functional overview 3.4 STM32L433xx Embedded Flash memory STM32L433xx devices feature up to 256 Kbyte of embedded Flash memory available for storing programs and data in single bank architecture. The Flash memory contains 128 pages of 2 Kbyte. Flexible protections can be configured thanks to option bytes: • Readout protection (RDP) to protect the whole memory.
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STM32L433xx Functional overview The whole non-volatile memory embeds the error correction code (ECC) feature supporting: 3.5 • single error detection and correction • double error detection. • The address of the ECC fail can be read in the ECC register Embedded SRAM STM32L433xx devices feature 64 Kbyte of embedded SRAM. This SRAM is split into two blocks: • 48 Kbyte mapped at address 0x2000 0000 (SRAM1) • 16 Kbyte located at address 0x1000 0000 with hardware parity check (SRAM2).
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Functional overview 3.7 STM32L433xx Boot modes At startup, BOOT0 pin or nSWBOOT0 option bit, and BOOT1 option bit are used to select one of three boot options: • Boot from user Flash • Boot from system memory • Boot from embedded SRAM BOOT0 value may come from the PH3-BOOT0 pin or from an option bit depending on the value of a user option bit to free the GPIO pad if needed.
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STM32L433xx • Functional overview VBAT = 1.55 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and backup registers (through power switch) when VDD is not present. Note: When the functions supplied by VDDA or VDDUSB are not used, these supplies should preferably be shorted to VDD. Note: If these supplies are tied to ground, the I/Os supplied by these power supplies are not 5 V tolerant (refer to Table 19: Voltage characteristics).
PAGE 22
Functional overview STM32L433xx (PVD) that monitors the VDD power supply and compares it to the VPVD threshold. An interrupt can be generated when VDD drops below the VPVD threshold and/or when VDD is higher than the VPVD threshold. The interrupt service routine can then generate a warning message and/or put the MCU into a safe state. The PVD is enabled by software.
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STM32L433xx 3.9.3 Functional overview Voltage regulator Two embedded linear voltage regulators supply most of the digital circuitries: the main regulator (MR) and the low-power regulator (LPR). • The MR is used in the Run and Sleep modes and in the Stop 0 mode. • The LPR is used in Low-Power Run, Low-Power Sleep, Stop 1 and Stop 2 modes. It is also used to supply the 16 Kbyte SRAM2 in Standby with SRAM2 retention.
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/224 Downloaded from Arrow.com. DocID028794 Rev 4 Stop 0 LPSleep Sleep LPRun Run Mode MR Range 2(8) MR Range 1(8) LPR SMPS range 2 Low MR range2 SMPS range 2 High MR range 1 LPR SMPS range 2 Low MR range2 SMPS range 2 High MR range 1 Regulator(1) No No No Yes Yes CPU OFF ON(4) ON(4) ON(4) ON(4) ON ON(7) ON(7) ON ON LSE LSI Any except PLL Any Any except PLL Any Flash SRAM Clocks Any interrupt or event Reset pin, all I/Os BOR, PVD, PVM RTC, LCD, IWDG COMPx (x=1..
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Downloaded from Arrow.com. LPR LPR Stop 1 Stop 2 Regulator Mode (1) No No CPU Off Off ON ON LSE LSI LSE LSI Flash SRAM Clocks Reset pin, all I/Os BOR, PVD, PVM RTC, LCD, IWDG COMPx (x=1..2) I2C3(10) LPUART1(9) LPTIM1 Reset pin, all I/Os BOR, PVD, PVM RTC, LCD, IWDG COMPx (x=1..2) USARTx (x=1...3)(9) LPUART1(9) I2Cx (x=1...3)(10) LPTIMx (x=1,2) USB_FS(11) SWPMI1(12) BOR, PVD, PVM RTC, LCD, IWDG COMPx (x=1,2) DACx (x=1,2) OPAMPx (x=1) USARTx (x=1...3)(9) LPUART1(9) I2Cx (x=1...
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/224 Downloaded from Arrow.com. OFF OFF LPR Regulator Power ed Off Power ed Off CPU Reset pin 5 I/Os (WKUPx)(14) RTC RTC *** All other peripherals are powered off. *** I/O configuration can be floating, pull-up or pulldown(14) Off Power ed Off Power ed Off Reset pin 5 I/Os (WKUPx)(13) BOR, RTC, IWDG LSE LSE LSI BOR, RTC, IWDG *** All other peripherals are powered off.
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STM32L433xx Functional overview By default, the microcontroller is in Run mode after a system or a power Reset. It is up to the user to select one of the low-power modes described below: • Sleep mode In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can wake up the CPU when an interrupt/event occurs. • Low-power run mode This mode is achieved with VCORE supplied by the low-power regulator to minimize the regulator's operating current.
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Functional overview • STM32L433xx Shutdown mode The Shutdown mode allows to achieve the lowest power consumption. The internal regulator is switched off so that the VCORE domain is powered off. The PLL, the HSI16, the MSI, the LSI and the HSE oscillators are also switched off. The RTC can remain active (Shutdown mode with RTC, Shutdown mode without RTC). The BOR is not available in Shutdown mode. No power voltage monitoring is possible in this mode, therefore the switch to Backup domain is not supported.
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STM32L433xx Functional overview Table 5.
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Functional overview STM32L433xx Table 5.
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STM32L433xx Functional overview Table 5. Functionalities depending on the working mode(1) (continued) - - - CRC calculation unit O O O O - - - - - - - - - GPIOs O O O O O O O O (9) 5 pins (11) 5 pins - Peripheral Run Sleep Lowpower run Lowpower sleep - (10) Wakeup capability Shutdown Wakeup capability Standby Wakeup capability Stop 2 Wakeup capability Stop 0/1 VBAT (10) 1. Legend: Y = Yes (Enable). O = Optional (Disable by default.
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Functional overview 3.10 STM32L433xx Interconnect matrix Several peripherals have direct connections between them. This allows autonomous communication between peripherals, saving CPU resources thus power supply consumption. In addition, these hardware connections allow fast and predictable latency. Depending on peripherals, these interconnections can operate in Run, Sleep, low-power run and sleep, Stop 0, Stop 1 and Stop 2 modes.
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STM32L433xx Functional overview Sleep Low-power run Low-power sleep Stop 0 / Stop 1 Stop 2 Interconnect source Run Table 6. STM32L433xx peripherals interconnect matrix (continued) TIMx External trigger Y Y Y Y - - LPTIMERx External trigger Y Y Y Y Y (1) ADCx DACx Conversion external trigger Y Y Y Y - - Interconnect destination Interconnect action Y GPIO 1. LPTIM1 only. DocID028794 Rev 4 33/224 55 Downloaded from Arrow.com.
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Functional overview 3.11 STM32L433xx Clocks and startup The clock controller (see Figure 3) distributes the clocks coming from different oscillators to the core and the peripherals. It also manages clock gating for low-power modes and ensures clock robustness. It features: 34/224 Downloaded from Arrow.com.
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STM32L433xx Functional overview interrupt is generated if enabled. LSE failure can also be detected and generated an interrupt. • Clock-out capability: – MCO: microcontroller clock output: it outputs one of the internal clocks for external use by the application – LSCO: low speed clock output: it outputs LSI or LSE in all low-power modes (except VBAT). Several prescalers allow to configure the AHB frequency, the high speed APB (APB2) and the low speed APB (APB1) domains.
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Functional overview STM32L433xx Figure 3. Clock tree WR ,:'* /6, 5& N+] /6&2 WR 57& DQG /&' 26& B287 /6( 26& N+] 26& B,1 /6( /6, +6( 0&2 ĺ WR 3:5 6<6&/. +6, 26&B287 +6( 26& 0+] 26&B,1 WR $+% EXV FRUH PHPRU\ DQG '0$ &ORFN VRXUFH FRQWURO +6, $+% 35(6& +6( &ORFN GHWHFWRU +&/. )&/. &RUWH[ IUHH UXQQLQJ FORFN WR &RUWH[ V\VWHP WLPHU 06, +6, 6<6&/. $3% 35(6& 3&/. WR $3% SHULSKHUDOV [ RU [ +6, 5& 0+] /6( +6, 6<6&/.
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STM32L433xx 3.12 Functional overview General-purpose inputs/outputs (GPIOs) Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog alternate functions. Fast I/O toggling can be achieved thanks to their mapping on the AHB2 bus.
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Functional overview STM32L433xx 3.14 Interrupts and events 3.14.1 Nested vectored interrupt controller (NVIC) The devices embed a nested vectored interrupt controller able to manage 16 priority levels, and handle up to 67 maskable interrupt channels plus the 16 interrupt lines of the Cortex®M4.
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STM32L433xx 3.15 Functional overview Analog to digital converter (ADC) The device embeds a successive approximation analog-to-digital converter with the following features: • 12-bit native resolution, with built-in calibration • 5.33 Msps maximum conversion rate with full resolution Down to 18.75 ns sampling time – Increased conversion rate for lower resolution (up to 8.88 Msps for 6-bit resolution) • Up to 16 external channels.
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Functional overview STM32L433xx Table 8. Temperature sensor calibration values 3.15.2 Calibration value name Description Memory address TS_CAL1 TS ADC raw data acquired at a temperature of 30 °C (± 5 °C), VDDA = VREF+ = 3.0 V (± 10 mV) 0x1FFF 75A8 - 0x1FFF 75A9 TS_CAL2 TS ADC raw data acquired at a temperature of 130 °C (± 5 °C), VDDA = VREF+ = 3.
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STM32L433xx Functional overview This digital interface supports the following features: • Up to two DAC output channels • 8-bit or 12-bit output mode • Buffer offset calibration (factory and user trimming) • Left or right data alignment in 12-bit mode • Synchronized update capability • Noise-wave generation • Triangular-wave generation • Dual DAC channel independent or simultaneous conversions • DMA capability for each channel • External triggers for conversion • Sample and hold low-p
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Functional overview 3.18 STM32L433xx Comparators (COMP) The STM32L433xx devices embed two rail-to-rail comparators with programmable reference voltage (internal or external), hysteresis and speed (low speed for low-power) and with selectable output polarity. The reference voltage can be one of the following: • External I/O • DAC output channels • Internal reference voltage or submultiple (1/4, 1/2, 3/4).
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STM32L433xx Functional overview The main features of the touch sensing controller are the following: • Proven and robust surface charge transfer acquisition principle • Supports up to 21 capacitive sensing channels • Up to 3 capacitive sensing channels can be acquired in parallel offering a very good response time • Spread spectrum feature to improve system robustness in noisy environments • Full hardware management of the charge transfer acquisition sequence • Programmable charge transfer freq
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Functional overview 3.23 STM32L433xx Timers and watchdogs The STM32L433xx includes one advanced control timers, up to five general-purpose timers, two basic timers, two low-power timers, two watchdog timers and a SysTick timer. The table below compares the features of the advanced control, general purpose and basic timers. Table 10.
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STM32L433xx 3.23.2 Functional overview General-purpose timers (TIM2, TIM15, TIM16) There are up to three synchronizable general-purpose timers embedded in the STM32L433xx (see Table 10 for differences). Each general-purpose timer can be used to generate PWM outputs, or act as a simple time base. • TIM2 It is a full-featured general-purpose timer: TIM2 has a 32-bit auto-reload up/downcounter and 32-bit prescaler.
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Functional overview STM32L433xx This low-power timer supports the following features: 3.23.5 • 16-bit up counter with 16-bit autoreload register • 16-bit compare register • Configurable output: pulse, PWM • Continuous/ one shot mode • Selectable software/hardware input trigger • Selectable clock source – Internal clock sources: LSE, LSI, HSI16 or APB clock – External clock source over LPTIM input (working even with no internal clock source running, used by pulse counter application).
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STM32L433xx 3.24 Functional overview Real-time clock (RTC) and backup registers The RTC is an independent BCD timer/counter. It supports the following features: • Calendar with subsecond, seconds, minutes, hours (12 or 24 format), week day, date, month, year, in BCD (binary-coded decimal) format. • Automatic correction for 28, 29 (leap year), 30, and 31 days of the month. • Two programmable alarms. • On-the-fly correction from 1 to 32767 RTC clock pulses.
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Functional overview 3.25 STM32L433xx Inter-integrated circuit interface (I2C) The device embeds 3 I2C. Refer to Table 11: I2C implementation for the features implementation. The I2C bus interface handles communications between the microcontroller and the serial I2C bus. It controls all I2C bus-specific sequencing, protocol, arbitration and timing. The I2C peripheral supports: • • I2C-bus specification and user manual rev.
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STM32L433xx 3.26 Functional overview Universal synchronous/asynchronous receiver transmitter (USART) The STM32L433xx devices have three embedded universal synchronous receiver transmitters (USART1, USART2 and USART3). These interfaces provide asynchronous communication, IrDA SIR ENDEC support, multiprocessor communication mode, single-wire half-duplex communication mode and have LIN Master/Slave capability. They provide hardware management of the CTS and RTS signals, and RS485 Driver Enable.
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Functional overview 3.27 STM32L433xx Low-power universal asynchronous receiver transmitter (LPUART) The device embeds one Low-Power UART. The LPUART supports asynchronous serial communication with minimum power consumption. It supports half duplex single wire communication and modem operations (CTS/RTS). It allows multiprocessor communication. The LPUART has a clock domain independent from the CPU clock, and can wakeup the system from Stop mode using baudrates up to 220 Kbaud.
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STM32L433xx 3.28 Functional overview Serial peripheral interface (SPI) Three SPI interfaces allow communication up to 40 Mbits/s in master and up to 24 Mbits/s slave modes, in half-duplex, full-duplex and simplex modes. The 3-bit prescaler gives 8 master mode frequencies and the frame size is configurable from 4 bits to 16 bits. The SPI interfaces support NSS pulse mode, TI mode and Hardware CRC calculation. All SPI interfaces can be served by the DMA controller. 3.
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Functional overview STM32L433xx Table 13. SAI implementation SAI features Support(1) I2S, LSB or MSB-justified, PCM/DSP, TDM, AC’97 X Mute mode X Stereo/Mono audio frame capability. X 16 slots X Data size configurable: 8-, 10-, 16-, 20-, 24-, 32-bit X FIFO Size X (8 Word) SPDIF X 1. X: supported 3.
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STM32L433xx Functional overview The CAN peripheral supports: • Supports CAN protocol version 2.0 A, B Active • Bit rates up to 1 Mbit/s • Transmission • • • 3.
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Functional overview STM32L433xx automatic trimming mode. The synchronization for this oscillator can be taken from the USB data stream itself (SOF signalization) which allows crystal less operation. 3.34 Clock recovery system (CRS) The STM32L433xx devices embed a special block which allows automatic trimming of the internal 48 MHz oscillator to guarantee its optimal accuracy over the whole device operational range.
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STM32L433xx Functional overview 3.36 Development support 3.36.1 Serial wire JTAG debug port (SWJ-DP) The ARM SWJ-DP interface is embedded, and is a combined JTAG and serial wire debug port that enables either a serial wire debug or a JTAG probe to be connected to the target.
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Pinouts and pin description 4 STM32L433xx Pinouts and pin description 9'' 966 3( 3( 3% 3% 3+ %227 3% 3% 3% 3% 3% 3' 3' 3' 3' 3' 3' 3' 3' 3& 3& 3& 3$ 3$ Figure 5.
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STM32L433xx Pinouts and pin description Figure 6.
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Pinouts and pin description STM32L433xx 9'' 966 9'' 3% 3% 3+ %227 3% 3% 3% 3% 3% 3& 3& 3& 3$ 3$ Figure 8.
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STM32L433xx Pinouts and pin description Figure 10.
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Pinouts and pin description STM32L433xx 9'' 966 3% 3% 3+ %227 3% 3% 3% 3% 3% 3$ 3$ Figure 12.
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STM32L433xx Pinouts and pin description Table 14. Legend/abbreviations used in the pinout table Name Abbreviation Definition Unless otherwise specified in brackets below the pin name, the pin function during and after reset is the same as the actual pin name Pin name S Supply pin I Input only pin Pin type I/O Input / output pin FT 5 V tolerant I/O TT 3.
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Pinouts and pin description STM32L433xx Table 15.
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STM32L433xx Pinouts and pin description Table 15.
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Pinouts and pin description STM32L433xx Table 15.
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STM32L433xx Pinouts and pin description Table 15.
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Pinouts and pin description STM32L433xx Table 15. STM32L433xx pin definitions (continued) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 21 21 E3 H4 29 28 G7 66/224 Downloaded from Arrow.com.
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STM32L433xx Pinouts and pin description Table 15.
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Pinouts and pin description STM32L433xx Table 15.
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STM32L433xx Pinouts and pin description Table 15.
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Pinouts and pin description STM32L433xx Table 15.
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STM32L433xx Pinouts and pin description Table 15.
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Pinouts and pin description STM32L433xx Table 15.
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STM32L433xx Pinouts and pin description Table 15.
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/224 Downloaded from Arrow.com. Port H - - PH3 - LPUART1 PH1 PH0 Port AF8 - - - CAN1/TSC AF9 - - - USB/QUADSPI AF10 - - - LCD AF11 - - - - SAI1 SDMMC1/ COMP1/ COMP2/ SWPMI1 - AF13 AF12 AF14 - - - TIM2/TIM15/ TIM16/LPTIM2 Table 17.
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STM32L433xx 5 Memory mapping Memory mapping Figure 14.
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Memory mapping STM32L433xx Table 18. STM32L433xx memory map and peripheral register boundary addresses(1) Bus AHB2 - AHB1 APB2 86/224 Downloaded from Arrow.com.
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STM32L433xx Memory mapping Table 18.
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Memory mapping STM32L433xx Table 18. STM32L433xx memory map and peripheral register boundary addresses(1) (continued) Bus APB1 Boundary address Downloaded from Arrow.com.
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STM32L433xx Electrical characteristics 6 Electrical characteristics 6.1 Parameter conditions Unless otherwise specified, all voltages are referenced to VSS. 6.1.1 Minimum and maximum values Unless otherwise specified, the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at TA = 25 °C and TA = TAmax (given by the selected temperature range).
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Electrical characteristics 6.1.6 STM32L433xx Power supply scheme Figure 17. Power supply scheme 9%$7 ĂĐŬƵƉ ĐŝƌĐƵŝƚƌǇ ;>^ ͕ Zd ͕ ĂĐŬƵƉ ƌĞŐŝƐƚĞƌƐͿ ϭ͘ϱϱ ʹ ϯ͘ϲ s WŽǁĞƌ ƐǁŝƚĐŚ 9'' 9&25( Q [ 9'' ZĞŐƵůĂƚŽƌ Khd Q [ Q) *3,2V /E [ ) /HYHO VKLIWHU 9'',2 ,2 ORJLF <ĞƌŶĞů ůŽŐŝĐ ; Wh͕ ŝŐŝƚĂů Θ DĞŵŽƌŝĞƐͿ Q [ 966 9''$ 9''$ 95() ϭϬ Ŷ& ) ϭϬϬ Ŷ& ) 95() 95() $'&V '$&V 23$03V &203V 95()%8) 966$ 06Y 9 Caution: 90/224 Downloaded from Arrow.com.
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STM32L433xx 6.1.7 Electrical characteristics Current consumption measurement Figure 18. Current consumption measurement scheme with and without external SMPS power supply ,''B86% ,''B86% 9''86% 9''86% ,''B9%$7 ,''B9%$7 9%$7 9%$7 ,'' ,'' ,''$ 6036 9'' 9'' 9'' ,''$ 9''$ 9''$ 06Y 9 The IDD_ALL parameters given in Table 26 to Table 48 represent the total MCU consumption including the current supplying VDD, VDDA, VDDUSB and VBAT. 6.
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Electrical characteristics STM32L433xx Table 19. Voltage characteristics(1) (continued) Symbol |∆VDDx| |VSSx-VSS| Ratings Min Max Unit Variations between different VDDX power pins of the same domain - 50 mV Variations between all the different ground pins(5) - 50 mV 1. All main power (VDD, VDDA, VDDUSB, VLCD, VBAT) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the permitted range. 2. VIN maximum must always be respected.
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STM32L433xx Electrical characteristics Table 21. Thermal characteristics Symbol TSTG TJ Ratings Storage temperature range Maximum junction temperature DocID028794 Rev 4 Value Unit –65 to +150 °C 150 °C 93/224 193 Downloaded from Arrow.com.
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Electrical characteristics STM32L433xx 6.3 Operating conditions 6.3.1 General operating conditions Table 22.
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STM32L433xx Electrical characteristics Table 22.
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Electrical characteristics 6.3.3 STM32L433xx Embedded reset and power control block characteristics The parameters given in Table 24 are derived from tests performed under the ambient temperature conditions summarized in Table 22: General operating conditions. Table 24. Embedded reset and power control block characteristics Symbol tRSTTEMPO(2) Downloaded from Arrow.com. Typ Max Unit - 250 400 μs Rising edge 1.62 1.66 1.7 Falling edge 1.6 1.64 1.69 Rising edge 2.06 2.1 2.
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STM32L433xx Electrical characteristics Table 24. Embedded reset and power control block characteristics (continued) Symbol Parameter Conditions(1) Min Typ Max Unit - - 1.1 1.6 µA - 1.18 1.22 1.26 V (3) IDD BOR (except BOR0) and (BOR_PVD)(2) PVD consumption from VDD VPVM1 VDDUSB peripheral voltage monitoring VPVM3 VDDA peripheral voltage monitoring Rising edge 1.61 1.65 1.69 Falling edge 1.6 1.64 1.68 VPVM4 VDDA peripheral voltage monitoring Rising edge 1.78 1.82 1.
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Electrical characteristics 6.3.4 STM32L433xx Embedded voltage reference The parameters given in Table 25 are derived from tests performed under the ambient temperature and supply voltage conditions summarized in Table 22: General operating conditions. Table 25. Embedded internal voltage reference Symbol VREFINT Parameter Conditions Internal reference voltage –40 °C < TA < +130 °C Min Typ Max Unit 1.182 1.212 1.
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STM32L433xx Electrical characteristics Figure 19. VREFINT versus temperature 9 0HDQ 0LQ DocID028794 Rev 4 0D[ & 06Y 9 99/224 193 Downloaded from Arrow.com.
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Electrical characteristics 6.3.5 STM32L433xx Supply current characteristics The current consumption is a function of several parameters and factors such as the operating voltage, ambient temperature, I/O pin loading, device software configuration, operating frequencies, I/O pin switching rate, program location in memory and executed binary code. The current consumption is measured as described in Figure 18: Current consumption measurement scheme with and without external SMPS power supply.
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Downloaded from Arrow.com. DocID028794 Rev 4 0.12 8.53 7.7 6.86 5.13 3.46 2.63 1.8 211 117 58.5 30 100 kHz 80 MHz 72 MHz 64 MHz Range 1 48 MHz 32 MHz 24 MHz 16 MHz 2 MHz 1 MHz 400 kHz 100 kHz 1. Guaranteed by characterization results, unless otherwise specified. 0.2 0.29 2 MHz 0.81 8 MHz 0.46 1.5 16 MHz 4 MHz 2.37 26 MHz 41.1 70.4 134 230 1.81 2.64 3.48 5.16 6.9 7.73 8.56 0.13 0.21 0.3 0.47 0.82 1.52 2.
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/224 Downloaded from Arrow.com. DocID028794 Rev 4 Supply current in Run mode IDD_ALL(Run) fHCLK = fHSE up to 48MHz included, bypass mode PLL ON above 48 MHz all peripherals disable - Conditions(1) 0.35 0.20 0.13 0.09 0.05 4 MHz 2 MHz 1 MHz 100 kHz 1.24 32 MHz 8 MHz 1.84 48 MHz 0.65 2.47 64 MHz 16 MHz 2.77 72 MHz 0.95 3.07 80 MHz 24 MHz 25 °C fHCLK 0.06 0.09 0.13 0.20 0.35 0.65 0.95 1.25 1.85 2.48 2.78 3.08 55 °C 0.07 0.11 0.15 0.22 0.38 0.67 0.97 1.28 1.
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Downloaded from Arrow.com. Supply current in fHCLK = fMSI Low-power all peripherals disable run IDD_ALL (Run) IDD_ALL (LPRun) 1.05 8 MHz DocID028794 Rev 4 4.56 3.45 2.48 310 157 72.6 32.3 32 MHz 24 MHz 16 MHz 2 MHz 1 MHz 400 kHz 100 kHz 1. Guaranteed by characterization results, unless otherwise specified. 6.36 Range 1 48 MHz 80 MHz 7.63 100 kHz 7.74 0.12 8.56 1 MHz 64 MHz 0.36 0.23 2 MHz 0.6 1.88 16 MHz 4 MHz 2.66 26 MHz 46 89 173 317 2.51 3.48 4.6 6.4 7.68 7.79 8.61 0.
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/224 Downloaded from Arrow.com. DocID028794 Rev 4 Supply current in Run mode IDD_ALL(Run) fHCLK = fHSE up to 48MHz included, bypass mode PLL ON above 48 MHz all peripherals disable - Conditions(1) 25 °C 3.08 2.78 2.74 2.29 1.64 1.24 0.89 0.45 0.26 0.16 0.10 0.05 fHCLK 80 MHz 72 MHz 64 MHz 48 MHz 32 MHz 24 MHz 16 MHz 8 MHz 4 MHz 2 MHz 1 MHz 100 kHz 0.06 0.11 0.16 0.27 0.46 0.90 1.25 1.65 2.30 2.76 2.80 3.10 55 °C 0.07 0.11 0.15 0.28 0.48 0.92 1.27 1.68 2.33 2.79 2.83 3.
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Downloaded from Arrow.com. fHCLK = fMSI all peripherals disable FLASH in power-down Supply current in low-power run mode DocID028794 Rev 4 Range 1 49.2 21.5 100 kHz 2 MHz 400 kHz 205 16 MHz 111 1.82 24 MHz 1 MHz 3.51 2.66 32 MHz 5.19 6.95 64 MHz 48 MHz 7.79 8.63 80 MHz 72 MHz 0.2 0.12 1 MHz 100 kHz 0.29 2 MHz 0.82 8 MHz 0.47 1.54 4 MHz 2.43 2.42 26 MHz 16 MHz 33.3 62.7 126 228 1.84 2.68 3.53 5.22 6.99 7.83 8.68 0.13 0.21 0.3 0.48 0.84 1.
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/224 Downloaded from Arrow.com. Parameter - Conditions(1) DocID028794 Rev 4 0.35 0.20 0.13 0.09 0.06 8 MHz 4 MHz 2 MHz 1 MHz 100 kHz 1.24 32 MHz 0.65 1.85 48 MHz 16 MHz 2.48 64 MHz 0.95 2.77 72 MHz 24 MHz 3.07 80 MHz 0.07 0.10 0.14 0.22 0.37 0.67 0.97 1.26 1.87 2.50 2.80 3.09 25 °C 55 °C fHCLK 0.11 0.14 0.18 0.26 0.41 0.70 1.01 1.31 1.91 2.55 2.84 3.15 85 °C TYP 0.18 0.21 0.25 0.33 0.47 0.77 1.08 1.38 2.00 2.62 2.93 3.22 0.32 0.36 0.39 0.
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STM32L433xx Electrical characteristics Table 32. Typical current consumption in Run and Low-power run modes, with different codes running from Flash, ART enable (Cache ON Prefetch OFF) Conditions Symbol Parameter Range 2 fHCLK = 26 MHz Code 25 °C Reduced code(1) 2.37 91 Coremark 2.69 103 Dhrystone 2.1 2.74 Fibonacci 2.58 99 2.30 88 Reduced code 8.53 107 Coremark 9.68 121 Dhrystone 2.1 9.76 Fibonacci 9.27 116 8.20 103 Reduced code 211 106 Coremark 251 126 Dhrystone 2.
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Electrical characteristics STM32L433xx 1. All values are obtained by calculation based on measurements done without SMPS and using following parameters: SMPS input = 3.3 V, SMPS efficiency = 85%, VDD12 = 1.10 V 2. Reduced code used for characterization results provided in Table 26, Table 28, Table 30. Table 34. Typical current consumption in Run, with different codes running from Flash, ART enable (Cache ON Prefetch OFF) and power supplied by external SMPS (VDD12 = 1.
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STM32L433xx Electrical characteristics Table 35.
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Electrical characteristics STM32L433xx Table 37. Typical current consumption in Run modes, with different codesrunning from Flash, ART disable and power supplied by external SMPS (VDD12 = 1.05 V) Conditions(1) IDD_ALL (Run) Parameter Supply current in Run mode TYP Voltage scaling fHCLK = fHSE up to 48 MHz included, bypass mode PLL ON above 48 MHz all peripherals fHCLK = 26 MHz Symbol Code 25 °C Reduced code(2) 1.05 TYP Unit 25 °C Unit 40 Coremark 0.96 Dhrystone 2.1 0.
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STM32L433xx Electrical characteristics Table 39. Typical current consumption in Run, with different codesrunning from SRAM1 and power supplied by external SMPS (VDD12 = 1.10 V) Conditions(1) IDD_ALL (Run) Parameter Supply current in Run mode Voltage scaling - fHCLK = fHSE up to 48 MHz included, bypass mode PLL ON above 48 MHz all peripherals disable fHCLK = 80 MHz fHCLK = 26 MHz Symbol TYP Code 25 °C Reduced code(2) 1.04 TYP Unit 25 °C Unit 40 Coremark 0.94 36 Dhrystone 2.1 1.
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/224 Downloaded from Arrow.com. DocID028794 Rev 4 IDD_ALL (Sleep) 0.11 2.23 2.02 1.82 1.34 0.93 0.73 0.53 71.8 45.0 27.0 22.8 72 MHz 64 MHz Range 1 48 MHz 32 MHz 24 MHz 16 MHz 2 MHz 1 MHz 400 kHz 100 kHz 0.13 1 MHz 80 MHz 0.16 2 MHz 8 MHz 0.20 0.46 0.29 16 MHz 4 MHz 0.68 26 MHz 30.9 40.7 57.3 80.7 0.55 0.75 0.95 1.36 1.84 2.04 2.25 0.13 0.15 0.17 0.21 0.30 0.48 0.69 25 °C 55 °C fHCLK 100 kHz Range 2 Voltage scaling 1.
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Downloaded from Arrow.com. Supply current in sleep mode, IDD_ALL(Sleep) fHCLK = fHSE up to 48 MHz included, bypass mode pll ON above 48 MHz all peripherals disable - Conditions(1) 0.48 0.33 0.26 0.19 48 MHz 32 MHz 24 MHz 16 MHz 0.07 0.06 0.05 2 MHz 1 MHz 100 kHz 0.13 0.65 64 MHz 0.09 0.73 72 MHz 4 MHz 0.80 80 MHz 8 MHz 25 °C fHCLK 0.06 0.06 0.07 0.09 0.13 0.20 0.27 0.34 0.49 0.66 0.73 0.81 55 °C 0.07 0.08 0.09 0.11 0.15 0.22 0.29 0.36 0.51 0.68 0.75 0.
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/224 Downloaded from Arrow.com. Supply current in Stop 2 mode, RTC enabled Supply current in Stop 2 mode, RTC disabled IDD_ALL (Stop 2) IDD_ALL (Stop 2 with RTC) Parameter Symbol DocID028794 Rev 4 1.45 1.69 1.3 1.39 1.5 1.76 1.41 1.49 1.61 3V 3.6 V 1.8 V 2.4 V 3V 3.6 V 1.8 V 2.4 V 3V 6.17 3.58 1.28 1.39 1.59 1.86 1.8 V 2.4 V 3V 3.6 V 3.45 3.1 2.93 2.81 3.67 1.83 RTC clocked by LSE quartz(4) in low drive mode, LCD disabled 2.9 3.09 1.36 3.63 3.25 3.08 2.96 3.42 3.11 2.95 2.
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Downloaded from Arrow.com. Parameter 3V 3V 3V Wakeup clock is MSI = 4 MHz, voltage Range 2. See (5). Wakeup clock is HSI16 = 16 MHz, voltage Range 1. See (5). VDD Wakeup clock is MSI = 48 MHz, voltage Range 1. See (5). - Conditions 1.54 1.52 1.85 - - - 25 °C 55 °C - - - 85 °C TYP - - - - - - - - - 105 °C 125 °C 25 °C - - - 55 °C 5. Wakeup with code execution from Flash. Average value given for a typical wakeup time as specified in Table 51: Low-power mode wakeup timings.
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/224 Downloaded from Arrow.com. Supply current in Stop 1 mode, RTC disabled IDD_ALL (Stop 1) RTC clocked by LSI - - - DocID028794 Rev 4 RTC clocked by LSE quartz(3) in low drive mode LCD disabled LCD disabled LCD enabled(2) LCD disabled LCD enabled(2) clocked by LSI LCD disabled - Conditions Supply current IDD_ALL in stop 1 (Stop 1 with mode, RTC) RTC enabled RTC clocked by LSE bypassed at 32768 Hz Parameter Symbol 13 13.6 4.82 4.93 5.05 5.31 4.7 4.95 2.4 V 3V 3.6 V 1.8 V 2.4 V 12.
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Downloaded from Arrow.com. Parameter - Wakeup clock MSI = 48 MHz, voltage Range 1. See (4). - Conditions MAX(1) 1.22 1.20 3V 1.14 - - - - - - - - - - - - - - - - - - 4. Wakeup with code execution from Flash. Average value given for a typical wakeup time as specified in Table 51: Low-power mode wakeup timings. 3. Based on characterization done with a 32.768 kHz crystal (MC306-G-06Q-32.768, manufacturer JFVNY) with two 6.8 pF loading capacitors.
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/224 Downloaded from Arrow.com. Supply current in Stop 0 mode, RTC disabled IDD_ALL (Stop 0) 108 110 111 114 1.8 V 2.4 V 3V 3.6 V 2. Guaranteed by test in production. 125 123 121 119 25 °C 55 °C VDD Conditions 1. Guaranteed by characterization results, unless otherwise specified. Parameter Symbol 163 161 160 158 85 °C TYP 227 224 223 221 355 352 349 347 142 139 136 133 105 °C 125 °C 25 °C Table 46.
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Downloaded from Arrow.com. IDD_ALL (Standby) IDD_ALL (Standby with RTC) Supply current in Standby mode (backup registers retained), RTC disabled Supply current in Standby mode (backup registers retained), RTC enabled Parameter Symbol DocID028794 Rev 4 219 364 142 249 1.8 V 2.4 V 548 715 281 388 535 836 1.8 V 2.4 V RTC clocked by LSE quartz (3) in low drive mode 3 V 3.6 V 1 048 423 670 404 742 3V 126 - - - 655 521 2.4 V - 865 342 1.8 V 978 3V 771 3.
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/224 Downloaded from Arrow.com. Supply current to be added in Standby mode when SRAM2 is retained Supply current during wakeup from Standby mode Parameter Wakeup clock is MSI = 4 MHz. See (5). - - Conditions 178 184 3V 3.
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Downloaded from Arrow.com. Supply current in Shutdown mode (backup registers retained) RTC enabled IDD_ALL (Shutdown with RTC) Wakeup clock is MSI = 4 MHz. See (3). RTC clocked by LSE quartz (2) in low drive mode RTC clocked by LSE bypassed at 32768 Hz - Conditions 744 3.
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/224 Downloaded from Arrow.com. RTC disabled - Conditions RTC enabled and clocked by LSE quartz(2) RTC enabled and Backup domain clocked by LSE supply current bypassed at 32768 Hz Parameter 345 455 591 3V 3.6 V 256 1.8 V 2.4 V 419 3.6 V 154 1.8 V 316 6 3.6 V 228 5 3V 3V 1 2.4 V 2.
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STM32L433xx Electrical characteristics I/O system current consumption The current consumption of the I/O system has two components: static and dynamic. I/O static current consumption All the I/Os used as inputs with pull-up generate current consumption when the pin is externally held low. The value of this current consumption can be simply computed by using the pull-up/pull-down resistors values given in Table 70: I/O static characteristics.
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Electrical characteristics STM32L433xx On-chip peripheral current consumption The current consumption of the on-chip peripherals is given in Table 50.
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STM32L433xx Electrical characteristics Table 50. Peripheral current consumption (continued) Range 1 Range 2 Low-power run and sleep RTCA 1.7 1.1 2.1 CRS 0.3 0.3 0.6 USB FS independent clock domain 2.9 N/A N/A USB FS clock domain 2.3 N/A N/A I2C1 independent clock domain 3.5 2.8 3.4 I2C1 clock domain 1.1 0.9 1.0 I2C2 independent clock domain 3.5 3.0 3.4 I2C2 clock domain 1.1 0.7 0.9 I2C3 independent clock domain 2.9 2.3 2.5 I2C3 clock domain 0.9 0.4 0.8 LCD 0.
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Electrical characteristics STM32L433xx Table 50. Peripheral current consumption (continued) Range 1 Range 2 Low-power run and sleep WWDG 0.5 0.5 0.5 All APB1 on 51.5 35.5 48.6 AHB to APB2(4) 1.0 0.9 0.9 FW 0.2 0.2 0.2 SAI1 independent clock domain 2.3 1.8 1.9 SAI1 clock domain 2.1 1.8 2.0 SDMMC1 independent clock domain 4.7 3.9 3.9 SDMMC1 clock domain 2.5 1.9 1.9 SPI1 1.8 1.6 1.7 SYSCFG/VREFBUF/COMP 0.6 0.5 0.6 TIM1 8.1 6.5 7.6 TIM15 3.7 3.0 3.4 TIM16 2.
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STM32L433xx Electrical characteristics Table 51.
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Electrical characteristics STM32L433xx Table 51. Low-power mode wakeup timings(1) (continued) Symbol Parameter Conditions Typ Max Wakeup clock MSI = 48 MHz 8.02 9.24 Wakeup clock HSI16 = 16 MHz 7.66 8.95 Wakeup clock MSI = 24 MHz 8.5 9.54 Wakeup clock HSI16 = 16 MHz 7.75 8.95 Wakeup clock MSI = 4 MHz 12.06 13.16 Wakeup clock MSI = 48 MHz 5.45 6.79 Wakeup clock HSI16 = 16 MHz 6.9 7.98 Wakeup clock MSI = 24 MHz 6.3 7.36 Wakeup clock HSI16 = 16 MHz 6.9 7.
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STM32L433xx 6.3.7 Electrical characteristics External clock source characteristics High-speed external user clock generated from an external source In bypass mode the HSE oscillator is switched off and the input pin is a standard GPIO. The external clock signal has to respect the I/O characteristics in Section 6.3.14. However, the recommended clock input waveform is shown in Figure 20: High-speed external clock source AC timing diagram. Table 54.
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Electrical characteristics STM32L433xx Low-speed external user clock generated from an external source In bypass mode the LSE oscillator is switched off and the input pin is a standard GPIO. The external clock signal has to respect the I/O characteristics in Section 6.3.14. However, the recommended clock input waveform is shown in Figure 21. Table 55.
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STM32L433xx Electrical characteristics High-speed external clock generated from a crystal/ceramic resonator The high-speed external (HSE) clock can be supplied with a 4 to 48 MHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on design simulation results obtained with typical external components specified in Table 56.
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Electrical characteristics Note: STM32L433xx For information on selecting the crystal, refer to the application note AN2867 “Oscillator design guide for ST microcontrollers” available from the ST website www.st.com. Figure 22. Typical application with an 8 MHz crystal 5HVRQDWRU ZLWK LQWHJUDWHG FDSDFLWRUV &/ 26&B,1 0+] UHVRQDWRU &/ 5(;7 I+6( 5) %LDV FRQWUROOHG JDLQ 26&B287 06 9 1. REXT value depends on the crystal characteristics.
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STM32L433xx Electrical characteristics 1. Guaranteed by design. 2. Refer to the note and caution paragraphs below the table, and to the application note AN2867 “Oscillator design guide for ST microcontrollers”. 3. tSU(LSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 kHz oscillation is reached.
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Electrical characteristics 6.3.8 STM32L433xx Internal clock source characteristics The parameters given in Table 58 are derived from tests performed under ambient temperature and supply voltage conditions summarized in Table 22: General operating conditions. The provided curves are characterization results, not tested in production. High-speed internal (HSI16) RC oscillator Table 58.
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STM32L433xx Electrical characteristics Figure 24. HSI16 frequency versus temperature 0+] PLQ PHDQ & PD[ 06Y 9 DocID028794 Rev 4 135/224 193 Downloaded from Arrow.com.
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Electrical characteristics STM32L433xx Multi-speed internal (MSI) RC oscillator Table 59. MSI oscillator characteristics(1) Symbol Parameter Conditions Min Typ Max Range 0 98.7 100 101.3 Range 1 197.4 200 202.6 Range 2 394.8 400 405.2 Range 3 789.6 800 810.4 Range 4 0.987 1 1.013 Range 5 1.974 2 2.026 Range 6 3.948 4 4.052 Range 7 7.896 8 8.104 Range 8 15.79 16 16.21 Range 9 23.69 24 24.31 Range 10 31.58 32 32.42 Range 11 47.38 48 48.62 Range 0 - 98.
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STM32L433xx Electrical characteristics Table 59. MSI oscillator characteristics(1) (continued) Symbol Parameter Conditions Min Typ VDD=1.62 V to 3.6 V -1.2 - VDD=2.4 V to 3.6 V -0.5 - VDD=1.62 V to 3.6 V -2.5 - VDD=2.4 V to 3.6 V -0.8 - VDD=1.62 V to 3.6 V -5 - VDD=2.4 V to 3.6 V -1.
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Electrical characteristics STM32L433xx Table 59. MSI oscillator characteristics(1) (continued) Symbol IDD(MSI)(6) Parameter MSI oscillator power consumption Conditions MSI and PLL mode Min Typ Max Range 0 - - 0.6 1 Range 1 - - 0.8 1.2 Range 2 - - 1.2 1.7 Range 3 - - 1.9 2.5 Range 4 - - 4.7 6 Range 5 - - 6.5 9 Range 6 - - 11 15 Range 7 - - 18.5 25 Range 8 - - 62 80 Range 9 - - 85 110 Range 10 - - 110 130 Range 11 - - 155 190 Unit µA 1.
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STM32L433xx Electrical characteristics Figure 25. Typical current consumption versus MSI frequency High-speed internal 48 MHz (HSI48) RC oscillator Table 60. HSI48 oscillator characteristics(1) Symbol Parameter fHSI48 HSI48 Frequency TRIM HSI48 user trimming step USER TRIM COVERAGE Conditions VDD=3.
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Electrical characteristics STM32L433xx Table 60. HSI48 oscillator characteristics(1) (continued) Symbol Parameter Conditions Min Typ Max Unit NT jitter Next transition jitter Accumulated jitter on 28 cycles(4) - - +/-0.15(2) - ns PT jitter Paired transition jitter Accumulated jitter on 56 cycles(4) - - +/-0.25(2) - ns 1. VDD = 3 V, TA = –40 to 125°C unless otherwise specified. 2. Guaranteed by design. 3. Guaranteed by characterization results. 4.
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STM32L433xx 6.3.9 Electrical characteristics PLL characteristics The parameters given in Table 62 are derived from tests performed under temperature and VDD supply voltage conditions summarized in Table 22: General operating conditions. Table 62. PLL, PLLSAI1 characteristics(1) Symbol fPLL_IN Parameter Conditions Min Typ Max Unit PLL input clock(2) - 4 - 16 MHz PLL input clock duty cycle - 45 - 55 % Voltage scaling Range 1 3.0968 - 80 Voltage scaling Range 2 3.
PAGE 142
Electrical characteristics 6.3.10 STM32L433xx Flash memory characteristics Table 63. Flash memory characteristics(1) Symbol Parameter Conditions Typ Max Unit tprog 64-bit programming time - 81.69 90.76 µs tprog_row one row (32 double word) programming time normal programming 2.61 2.90 fast programming 1.91 2.12 tprog_page one page (2 Kbyte) programming time normal programming 20.91 23.24 fast programming 15.29 16.98 22.02 24.47 normal programming 5.35 5.
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STM32L433xx 6.3.11 Electrical characteristics EMC characteristics Susceptibility tests are performed on a sample basis during device characterization. Functional EMS (electromagnetic susceptibility) While a simple application is executed on the device (toggling 2 LEDs through I/O ports). the device is stressed by two electromagnetic events until a failure occurs.
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Electrical characteristics STM32L433xx Prequalification trials Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1 second. To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015).
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STM32L433xx Electrical characteristics Static latch-up Two complementary static tests are required on six parts to assess the latch-up performance: • A supply overvoltage is applied to each power supply pin. • A current injection is applied to each input, output and configurable I/O pin. These tests are compliant with EIA/JESD 78A IC latch-up standard. Table 68. Electrical sensitivities Symbol LU 6.3.
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Electrical characteristics 6.3.14 STM32L433xx I/O port characteristics General input/output characteristics Unless otherwise specified, the parameters given in Table 70 are derived from tests performed under the conditions summarized in Table 22: General operating conditions. All I/Os are designed as CMOS- and TTL-compliant. Table 70. I/O static characteristics Symbol VIL(1) VIH(1) Vhys(3) Parameter Max - - 0.3xVDDIOx (2) I/O input low level voltage 1.62 V
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STM32L433xx Electrical characteristics Table 70. I/O static characteristics (continued) Symbol Parameter Conditions RPD Weak pull-down VIN = VDDIOx equivalent resistor(8) CIO I/O pin capacitance Min Typ Max Unit 25 40 55 kΩ - 5 - pF - 1. Refer to Figure 27: I/O input characteristics. 2. Tested in production. 3. Guaranteed by design. 4. This value represents the pad leakage of the IO itself.
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Electrical characteristics STM32L433xx In the user application, the number of I/O pins which can drive current must be limited to respect the absolute maximum rating specified in Section 6.2: • The sum of the currents sourced by all the I/Os on VDDIOx, plus the maximum consumption of the MCU sourced on VDD, cannot exceed the absolute maximum rating ΣIVDD (see Table 19: Voltage characteristics).
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STM32L433xx Electrical characteristics Unless otherwise specified, the parameters given are derived from tests performed under the ambient temperature and supply voltage conditions summarized in Table 22: General operating conditions. Table 72. I/O AC characteristics(1)(2) Speed Symbol Fmax Parameter Maximum frequency 00 Tr/Tf Fmax Output rise and fall time Maximum frequency 01 Tr/Tf Output rise and fall time Conditions Min Max C=50 pF, 2.7 V≤VDDIOx≤3.6 V - 5 C=50 pF, 1.62 V≤VDDIOx≤2.
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Electrical characteristics STM32L433xx Table 72. I/O AC characteristics(1)(2) (continued) Speed Symbol Fmax Parameter Maximum frequency 10 Tr/Tf Fmax Output rise and fall time Maximum frequency 11 Tr/Tf Fm+ Fmax Tf Output rise and fall time Maximum frequency (4) Output fall time Conditions Min Max C=50 pF, 2.7 V≤VDDIOx≤3.6 V - 50 C=50 pF, 1.62 V≤VDDIOx≤2.7 V - 25 C=50 pF, 1.08 V≤VDDIOx≤1.62 V - 5 C=10 pF, 2.7 V≤VDDIOx≤3.6 V - 100(3) C=10 pF, 1.62 V≤VDDIOx≤2.7 V - 37.
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STM32L433xx Electrical characteristics Figure 28. I/O AC characteristics definition(1) W I ,2 RXW W U ,2 RXW 7 0D[LPXP IUHTXHQF\ LV DFKLHYHG LI W W U I 7 DQG LI WKH GXW\ F\FOH LV ZKHQ ORDGHG E\ WKH VSHFLILHG FDSDFLWDQFH 06 9 1. Refer to Table 72: I/O AC characteristics. 6.3.15 NRST pin characteristics The NRST pin input driver uses the CMOS technology. It is connected to a permanent pullup resistor, RPU.
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Electrical characteristics STM32L433xx Figure 29. Recommended NRST pin protection ([WHUQDO UHVHW FLUFXLW 9'' 1567 538 ,QWHUQDO UHVHW )LOWHU ) 06 9 1. The reset network protects the device against parasitic resets. 2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in Table 73: NRST pin characteristics. Otherwise the reset will not be taken into account by the device. 3.
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STM32L433xx 6.3.17 Electrical characteristics Analog-to-Digital converter characteristics Unless otherwise specified, the parameters given in Table 75 are preliminary values derived from tests performed under ambient temperature, fPCLK frequency and VDDA supply voltage conditions summarized in Table 22: General operating conditions. Note: It is recommended to perform a calibration after each power-up. Table 75.
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Electrical characteristics STM32L433xx Table 75. ADC characteristics(1) (2) (continued) Symbol Parameter tLATR Trigger conversion latency Regular and injected channels without conversion abort Conditions Min Typ Max CKMODE = 00 1.5 2 2.5 CKMODE = 01 - - 2.0 CKMODE = 10 - - 2.25 CKMODE = 11 - - 2.125 2.5 3 3.5 - - 3.0 - - 3.25 - - 3.125 0.03125 - 8.00625 µs - 2.5 - 640.5 1/fADC - - - 20 µs 0.1875 - 8.
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STM32L433xx Electrical characteristics Table 76. Maximum ADC RAIN(1)(2) Resolution 12 bits 10 bits 8 bits 6 bits Sampling cycle @80 MHz Sampling time [ns] @80 MHz 2.5 RAIN max (Ω) Fast channels(3) Slow channels(4) 31.25 100 N/A 6.5 81.25 330 100 12.5 156.25 680 470 24.5 306.25 1500 1200 47.5 593.75 2200 1800 92.5 1156.25 4700 3900 247.5 3093.75 12000 10000 640.5 8006.75 39000 33000 2.5 31.25 120 N/A 6.5 81.25 390 180 12.5 156.25 820 560 24.5 306.
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Electrical characteristics STM32L433xx 2. The I/O analog switch voltage booster is enable when VDDA < 2.4 V (BOOSTEN = 1 in the SYSCFG_CFGR1 when VDDA < 2.4V). It is disable when VDDA ≥ 2.4 V. 3. Fast channels are: PC0, PC1, PC2, PC3, PA0, PA1. 4. Slow channels are: all ADC inputs except the fast channels. 156/224 Downloaded from Arrow.com.
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STM32L433xx Electrical characteristics Table 77. ADC accuracy - limited test conditions 1(1)(2)(3) Symbol Parameter ET Total unadjusted error EO Conditions(4) Single ended Differential Single ended Offset error Differential Single ended EG Gain error Differential ED EL Differential linearity ADC clock frequency ≤ error 80 MHz, Sampling rate ≤ 5.
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Electrical characteristics STM32L433xx Table 77. ADC accuracy - limited test conditions 1(1)(2)(3) (continued) Symbol THD Conditions(4) Parameter Total harmonic distortion ADC clock frequency ≤ Single 80 MHz, ended Sampling rate ≤ 5.33 Msps, VDDA = VREF+ = 3 V, Differential TA = 25 °C Min Typ Max Unit Fast channel (max speed) - -74 -73 Slow channel (max speed) - -74 -73 Fast channel (max speed) - -79 -76 Slow channel (max speed) - -79 -76 dB 1. Guaranteed by design. 2.
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STM32L433xx Electrical characteristics Table 78. ADC accuracy - limited test conditions 2(1)(2)(3) Symbol Parameter ET Total unadjusted error EO Conditions(4) Single ended Differential Single ended Offset error Differential Single ended EG Gain error Differential ED EL Differential linearity error ADC clock frequency ≤ 80 MHz, Sampling rate ≤ 5.
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Electrical characteristics STM32L433xx Table 78. ADC accuracy - limited test conditions 2(1)(2)(3) (continued) Symbol THD Conditions(4) Parameter Total harmonic distortion Fast channel (max speed) Single ADC clock frequency ≤ ended Slow channel (max speed) 80 MHz, Sampling rate ≤ 5.33 Msps, Fast channel (max speed) Differential 2 V ≤ VDDA Slow channel (max speed) Min Typ Max Unit - -74 -65 - -74 -67 - -79 -70 - -79 -71 dB 1. Guaranteed by design. 2.
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STM32L433xx Electrical characteristics Table 79. ADC accuracy - limited test conditions 3(1)(2)(3) Symbol Parameter ET Total unadjusted error EO Conditions(4) Single ended Differential Single ended Offset error Differential Single ended EG Gain error Differential ED EL Differential linearity ADC clock frequency ≤ error 80 MHz, Sampling rate ≤ 5.33 Msps, 1.65 V ≤ VDDA = VREF+ ≤ 3.
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Electrical characteristics STM32L433xx Table 79. ADC accuracy - limited test conditions 3(1)(2)(3) (continued) Symbol THD Conditions(4) Parameter Total harmonic distortion ADC clock frequency ≤ Single 80 MHz, ended Sampling rate ≤ 5.33 Msps, 1.65 V ≤ VDDA = VREF+ ≤ Differential 3.6 V, Voltage scaling Range 1 Min Typ Max Unit Fast channel (max speed) - -69 -67 Slow channel (max speed) - -71 -67 Fast channel (max speed) - -72 -71 Slow channel (max speed) - -72 -71 dB 1.
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STM32L433xx Electrical characteristics Table 80. ADC accuracy - limited test conditions 4(1)(2)(3) Symbol Parameter ET Total unadjusted error EO Conditions(4) Single ended Differential Single ended Offset error Differential Single ended EG Gain error Differential ED EL Differential linearity ADC clock frequency ≤ error 26 MHz, 1.65 V ≤ VDDA = VREF+ ≤ 3.
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Electrical characteristics STM32L433xx Table 80. ADC accuracy - limited test conditions 4(1)(2)(3) (continued) Symbol THD Conditions(4) Parameter ADC clock frequency ≤ 26 MHz, 1.65 V ≤ VDDA = VREF+ ≤ 3.6 V, Voltage scaling Range 2 Total harmonic distortion Single ended Differential Min Typ Max Unit Fast channel (max speed) - -71 -69 Slow channel (max speed) - -71 -69 Fast channel (max speed) - -73 -72 Slow channel (max speed) - -73 -72 dB 1. Guaranteed by design. 2.
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STM32L433xx Electrical characteristics Figure 31. Typical connection diagram using the ADC 9''$ 97 5$,1 9$,1 6DPSOH DQG KROG $'& FRQYHUWHU 5$'& $,1[ &SDUDVLWLF 97 ,ONJ ELW FRQYHUWHU &$'& 06 9 1. Refer to Table 75: ADC characteristics for the values of RAIN and CADC. 2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad capacitance (refer to Table 70: I/O static characteristics for the value of the pad capacitance).
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Electrical characteristics 6.3.18 STM32L433xx Digital-to-Analog converter characteristics Table 81. DAC characteristics(1) Symbol VDDA VREF+ VREF- Parameter Analog supply voltage for DAC ON Positive reference voltage Conditions Min Typ DAC output buffer OFF, DAC_OUT pin not connected (internal connection only) 1.71 - Other modes 1.80 - DAC output buffer OFF, DAC_OUT pin not connected (internal connection only) 1.71 - Other modes 1.80 Negative reference voltage Max 3.
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STM32L433xx Electrical characteristics Table 81. DAC characteristics(1) (continued) Symbol TW_to_W tSAMP Parameter Conditions Typ Max Unit - - µs - 0.7 3.5 - 10.5 18 - 2 3.5 µs - - -(3) nA 5.2 7 8.8 pF 50 - - µs VREF+ = 3.6 V - 1500 - VREF+ = 1.8 V - 750 - No load, middle code (0x800) - 315 500 No load, worst code (0xF1C) - 450 670 No load, middle code (0x800) - - 0.
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Electrical characteristics STM32L433xx Table 81.
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STM32L433xx Electrical characteristics Table 82. DAC accuracy(1) .
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Electrical characteristics STM32L433xx Table 82. DAC accuracy(1) (continued) Symbol Parameter SINAD Signal-to-noise and distortion ratio ENOB Effective number of bits Conditions Min Typ Max DAC output buffer ON CL ≤ 50 pF, RL ≥ 5 kΩ, 1 kHz - 70.4 - DAC output buffer OFF CL ≤ 50 pF, no RL, 1 kHz - 71 - DAC output buffer ON CL ≤ 50 pF, RL ≥ 5 kΩ, 1 kHz - 11.4 - DAC output buffer OFF CL ≤ 50 pF, no RL, 1 kHz - Unit dB bits 11.5 - 1. Guaranteed by design. 2.
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STM32L433xx 6.3.19 Electrical characteristics Voltage reference buffer characteristics Table 83. VREFBUF characteristics(1) Symbol Parameter Conditions Normal mode VDDA VREFBUF_ OUT Analog supply voltage Voltage reference output Degraded mode(2) Normal mode Degraded mode(2) Min Typ Max VRS = 0 2.4 - 3.6 VRS = 1 2.8 - 3.6 VRS = 0 1.65 - 2.4 VRS = 1 1.65 - 2.8 2.048 2.049(3) (3) VRS = 0 2.046 VRS = 1 2.498(3) 2.5 2.
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Electrical characteristics STM32L433xx Table 83. VREFBUF characteristics(1) (continued) Symbol Parameter VREFBUF IDDA(VREF consumption BUF) from VDDA Conditions Min Typ Max Iload = 0 µA - 16 25 Iload = 500 µA - 18 30 Iload = 4 mA - 35 50 Unit µA 1. Guaranteed by design, unless otherwise specified. 2. In degraded mode, the voltage reference buffer can not maintain accurately the output voltage which will follow (VDDA drop voltage). 3. Guaranteed by test in production. 4.
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STM32L433xx 6.3.20 Electrical characteristics Comparator characteristics Table 84. COMP characteristics(1) Symbol Conditions Min Typ Max Analog supply voltage - 1.62 - 3.6 Comparator input voltage range - 0 - VDDA V VBG(2) Scaler input voltage - VSC Scaler offset voltage - VDDA VIN IDDA(SCALER) Parameter VREFINT - ±5 ±10 mV BRG_EN=0 (bridge disable) - 200 300 nA BRG_EN=1 (bridge enable) - 0.8 1 µA - 100 200 µs VDDA ≥ 2.7 V - - 5 VDDA < 2.
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Electrical characteristics STM32L433xx Table 84.
PAGE 175
STM32L433xx Electrical characteristics Table 85.
PAGE 176
Electrical characteristics STM32L433xx Table 85.
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STM32L433xx Electrical characteristics Table 85.
PAGE 178
Electrical characteristics 6.3.23 STM32L433xx VBAT monitoring characteristics Table 87. VBAT monitoring characteristics Symbol Parameter Min Typ Max Unit R Resistor bridge for VBAT - 39 - kΩ Q Ratio on VBAT measurement - 3 - - Error on Q -10 - 10 % ADC sampling time when reading the VBAT 12 - - µs Er (1) (1) tS_vbat 1. Guaranteed by design. Table 88. VBAT charging characteristics Symbol RBC 178/224 Downloaded from Arrow.com.
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STM32L433xx 6.3.24 Electrical characteristics LCD controller characteristics The devices embed a built-in step-up converter to provide a constant LCD reference voltage independently from the VDD voltage. An external capacitor Cext must be connected to the VLCD pin to decouple this converter. Table 89. LCD controller characteristics(1) Symbol Parameter Conditions Min Typ Max VLCD LCD external voltage - - 3.6 VLCD0 LCD internal reference voltage 0 - 2.
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Electrical characteristics STM32L433xx 1. Guaranteed by design. 2. LCD enabled with 3 V internal step-up active, 1/8 duty, 1/4 bias, division ratio= 64, all pixels active, no LCD connected. 6.3.25 Timer characteristics The parameters given in the following tables are guaranteed by design. Refer to Section 6.3.14: I/O port characteristics for details on the input/output alternate function characteristics (output compare, input capture, external clock, PWM output). Table 90.
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STM32L433xx Electrical characteristics Table 92. WWDG min/max timeout value at 80 MHz (PCLK) 6.3.26 Prescaler WDGTB Min timeout value Max timeout value 1 0 0.0512 3.2768 2 1 0.1024 6.5536 4 2 0.2048 13.1072 8 3 0.4096 26.2144 Unit ms Communication interfaces characteristics I2C interface characteristics The I2C interface meets the timings requirements of the I2C-bus specification and user manual rev.
PAGE 182
Electrical characteristics STM32L433xx SPI characteristics Unless otherwise specified, the parameters given in Table 94 for SPI are derived from tests performed under the ambient temperature, fPCLKx frequency and supply voltage conditions summarized in Table 22: General operating conditions. • Output speed is set to OSPEEDRy[1:0] = 11 • Capacitive load C = 30 pF • Measurement points are done at CMOS levels: 0.5 ₓ VDD Refer to Section 6.3.
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STM32L433xx Electrical characteristics Table 94. SPI characteristics(1) (continued) Symbol tv(SO) Parameter Data output valid time tv(MO) th(SO) Data output hold time th(MO) Conditions Min Typ Max Slave mode 2.7 < VDD < 3.6 V Voltage Range 1 - 12.5 13.5 Slave mode 1.71 < VDD < 3.6 V Voltage Range 1 - 12.5 24 Slave mode 1.71 < VDD < 3.6 V Voltage Range 2 - 12.5 33 Master mode - 4.5 6 Slave mode 7 - - Master mode 0 - - Unit ns ns 1.
PAGE 184
Electrical characteristics STM32L433xx Figure 34. SPI timing diagram - slave mode and CPHA = 1 166 LQSXW WF 6&. WVX 166 WZ 6&.+ WD 62 WZ 6&./ WI 6&. WK 166 6&. LQSXW &3+$ &32/ &3+$ &32/ 0,62 RXWSXW WY 62 WK 62 )LUVW ELW 287 WVX 6, 1H[W ELWV 287 WU 6&. WGLV 62 /DVW ELW 287 WK 6, 026, LQSXW )LUVW ELW ,1 1H[W ELWV ,1 /DVW ELW ,1 06Y 9 1. Measurement points are done at CMOS levels: 0.3 VDD and 0.7 VDD. Figure 35. SPI timing diagram - master mode +LJK 166 LQSXW 6&.
PAGE 185
STM32L433xx Electrical characteristics Quad SPI characteristics Unless otherwise specified, the parameters given in Table 95 and Table 96 for Quad SPI are derived from tests performed under the ambient temperature, fAHB frequency and VDD supply voltage conditions summarized in Table 22: General operating conditions, with the following configuration: • Output speed is set to OSPEEDRy[1:0] = 11 • Capacitive load C = 15 or 20 pF • Measurement points are done at CMOS levels: 0.5 ₓ VDD Refer to Section 6.3.
PAGE 186
Electrical characteristics STM32L433xx Table 96. QUADSPI characteristics in DDR mode(1) Symbol FCK 1/t(CK) tw(CKH) tw(CKL) Parameter Quad SPI clock frequency Quad SPI clock high and low time Conditions Min Typ Max 1.71 < VDD < 3.6 V, CLOAD = 20 pF Voltage Range 1 - - 40 2 < VDD < 3.6 V, CLOAD = 20 pF Voltage Range 1 - - 48 1.71 < VDD < 3.6 V, CLOAD = 15 pF Voltage Range 1 - - 48 1.71 < VDD < 3.
PAGE 187
STM32L433xx Electrical characteristics Figure 36. Quad SPI timing diagram - SDR mode WU &. &ORFN W &. WZ &.+ WY 287 WZ &./ WI &. WK 287 'DWD RXWSXW ' ' WV ,1 'DWD LQSXW ' WK ,1 ' ' ' 06Y 9 Figure 37. Quad SPI timing diagram - DDR mode WU &. &ORFN 'DWD RXWSXW W &. WYI 287 WZ &.+ WKU 287 ' WYU 287 ' ' WZ &./ WKI 287 ' WVI ,1 WKI ,1 'DWD LQSXW ' ' WI &. ' ' WVU ,1 WKU ,1 ' ' ' ' 06Y 9 DocID028794 Rev 4 187/224 193 Downloaded from Arrow.com.
PAGE 188
Electrical characteristics STM32L433xx SAI characteristics Unless otherwise specified, the parameters given in Table 97 for SAI are derived from tests performed under the ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized inTable 22: General operating conditions, with the following configuration: • Output speed is set to OSPEEDRy[1:0] = 10 • Capacitive load C = 30 pF • Measurement points are done at CMOS levels: 0.5 ₓ VDD Refer to Section 6.3.
PAGE 189
STM32L433xx Electrical characteristics Table 97. SAI characteristics(1) (continued) Symbol tv(SD_B_ST) th(SD_B_ST) tv(SD_A_MT) th(SD_A_MT) Parameter Conditions Data output valid time Data output hold time Data output valid time Data output hold time Min Max Slave transmitter (after enable edge) 2.7 ≤ VDD ≤ 3.6 - 22 Slave transmitter (after enable edge) 1.71 ≤ VDD ≤ 3.6 - 34 Slave transmitter (after enable edge) 10 - Master transmitter (after enable edge) 2.7 ≤ VDD ≤ 3.
PAGE 190
Electrical characteristics STM32L433xx Figure 39.
PAGE 191
STM32L433xx Electrical characteristics Table 98. SD / MMC dynamic characteristics, VDD=2.7 V to 3.6 V(1) (continued) Symbol Parameter Conditions Min Typ Max Unit CMD, D outputs (referenced to CK) in SD default mode tOVD Output valid default time SD fPP = 50 MHz - 2 3 ns tOHD Output hold default time SD fPP = 50 MHz 0 - - ns 1. Guaranteed by characterization results. Table 99. eMMC dynamic characteristics, VDD = 1.71 V to 1.
PAGE 192
Electrical characteristics STM32L433xx Figure 41. SD default mode #+ T/6$ T/($ $ #-$ OUTPUT AI USB characteristics The STM32L433xx USB interface is fully compliant with the USB specification version 2.0 and is USB-IF certified (for Full-speed device operation). Table 100. USB electrical characteristics(1) Symbol Min Typ Max Unit 3.0(2) - 3.
PAGE 193
STM32L433xx Electrical characteristics Table 101. SWPMI electrical characteristics (continued) Symbol tSWPBIT Parameter SWP bit duration Conditions Min Typ VCORE voltage range 1 500 - - VCORE voltage range 2 620 - - DocID028794 Rev 4 Max Unit ns 193/224 193 Downloaded from Arrow.com.
PAGE 194
Package information 7 STM32L433xx Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. 7.1 LQFP100 package information Figure 42. LQFP100 - 100-pin, 14 x 14 mm low-profile quad flat package outline MM C ! ! ! 3%!4).' 0,!.% # '!5'% 0,!.
PAGE 195
STM32L433xx Package information Table 102. LQPF100 - 100-pin, 14 x 14 mm low-profile quad flat package mechanical data (continued) inches(1) millimeters Symbol Min Typ Max Min Typ Max A2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 D 15.800 16.000 16.200 0.6220 0.6299 0.6378 D1 13.800 14.000 14.200 0.5433 0.5512 0.5591 D3 - 12.000 - - 0.4724 - E 15.800 16.000 16.200 0.6220 0.6299 0.
PAGE 196
Package information STM32L433xx Device marking The following figure gives an example of topside marking orientation versus pin 1 identifier location. Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. Figure 44. LQFP100 marking (package top view) 3URGXFW LGHQWLILFDWLRQ 670 / 2SWLRQDO JDWH PDUN 9&7 $ 5HYLVLRQ FRGH 'DWH FRGH < :: 3LQ LQGHQWLILHU 06Y 9 1.
PAGE 197
STM32L433xx 7.2 Package information UFBGA100 package information Figure 45. UFBGA100 - 100-ball, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array package outline = 6HDWLQJ SODQH GGG = $ $ $ $ $ ( $ EDOO $ EDOO LGHQWLILHU LQGH[ DUHD = H ; ( $ = ' ' H < 0 %27720 9,(: E EDOOV HHH 0 = < ; III 0 = 723 9,(: $ & B0(B9 1. Drawing is not to scale. Table 103. UFBGA100 - 100-ball, 7 x 7 mm, 0.
PAGE 198
Package information STM32L433xx Table 103. UFBGA100 - 100-ball, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array package mechanical data (continued) inches(1) millimeters Symbol Min. Typ. Max. Min. Typ. Max. ddd - - 0.080 - - 0.0031 eee - - 0.150 - - 0.0059 fff - - 0.050 - - 0.0020 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 46. UFBGA100 - 100-ball, 7 x 7 mm, 0.
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STM32L433xx Package information Figure 47. UFBGA100 marking (package top view) 3URGXFW LGHQWLILFDWLRQ 670 / 9&, < :: 'DWH FRGH $ 3LQ LGHQWLILHU 06Y 9 1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production.
PAGE 200
Package information 7.3 STM32L433xx LQFP64 package information Figure 48. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package outline PP *$8*( 3/$1( F $ $ $ 6($7,1* 3/$1( & $ FFF & ' ' ' . / / 3,1 ,'(17,),&$7,21 ( ( ( E H :B0(B9 1. Drawing is not to scale. Table 105. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package mechanical data inches(1) millimeters Symbol 200/224 Downloaded from Arrow.com.
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STM32L433xx Package information Table 105. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package mechanical data (continued) inches(1) millimeters Symbol Min Typ Max Min Typ Max E3 - 7.500 - - 0.2953 - e - 0.500 - - 0.0197 - K 0° 3.5° 7° 0° 3.5° 7° L 0.450 0.600 0.750 0.0177 0.0236 0.0295 L1 - 1.000 - - 0.0394 - ccc - - 0.080 - - 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 49.
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Package information STM32L433xx Figure 50. LQFP64 marking (package top view) 5HYLVLRQ FRGH $ 3URGXFW LGHQWLILFDWLRQ 670 / 5&7 < :: 'DWH FRGH 3LQ LGHQWLILHU 06Y 9 1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use.
PAGE 203
STM32L433xx Package information Table 106. UFBGA64 – 64-ball, 5 x 5 mm, 0.5 mm pitch ultra profile fine pitch ball grid array package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A 0.460 0.530 0.600 0.0181 0.0209 0.0236 A1 0.050 0.080 0.110 0.0020 0.0031 0.0043 A2 0.400 0.450 0.500 0.0157 0.0177 0.0197 A3 0.080 0.130 0.180 0.0031 0.0051 0.0071 A4 0.270 0.320 0.370 0.0106 0.0126 0.0146 b 0.170 0.280 0.330 0.0067 0.0110 0.0130 D 4.
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Package information STM32L433xx Table 107. UFBGA64 recommended PCB design rules (0.5 mm pitch BGA) (continued) Dimension Recommended values Stencil thickness Between 0.100 mm and 0.125 mm Pad trace width 0.100 mm Device marking The following figure gives an example of topside marking orientation versus ball A1 identifier location. Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. Figure 53.
PAGE 205
STM32L433xx 7.5 Package information WLCSP64 package information Figure 54. WLCSP64 - 64-ball, 3.141 x 3.127 mm, 0.35 mm pitch wafer level chip scale package outline H EEE = ) * $ 'HWDLO $ H H + * H $ $ $ ) %XPS VLGH 6LGH YLHZ ' %XPS $ HHH = ( $ 2ULHQWDWLRQ UHIHUHQFH E FFF = ; < GGG = = 6HDWLQJ SODQH DDD [ :DIHU EDFN VLGH 'HWDLO $ URWDWHG :/&63 B$ B0(B9 1. Drawing is not to scale. Table 108. WLCSP64 - 64-ball, 3.141 x 3.127 mm, 0.
PAGE 206
Package information STM32L433xx Table 108. WLCSP64 - 64-ball, 3.141 x 3.127 mm, 0.35 mm pitch wafer level chip scale package mechanical data (continued) inches(1) millimeters Symbol Min Typ Max Min Typ Max (3) 0.190 0.220 0.250 0.0075 0.0087 0.0098 D 3.106 3.141 3.176 0.1223 0.1237 0.1250 E 3.092 3.127 3.162 0.1217 0.1231 0.1245 e - 0.350 - - 0.0138 - e1 - 2.450 - - 0.0965 - e2 - 2.450 - - 0.0965 - F - 0.3455 - - 0.0136 - G - 0.3385 - - 0.
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STM32L433xx Package information Device marking The following figure gives an example of topside marking orientation versus ball A1 identifier location. Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. Figure 56. WLCSP64 marking (package top view) 3LQ LGHQWLILHU 3URGXFW LGHQWLILFDWLRQ / 5& < :: $ 5HYLVLRQ FRGH 'DWH FRGH 06Y 9 1.
PAGE 208
Package information 7.6 STM32L433xx WLCSP49 package information Figure 57. WLCSP49 - 49-ball, 3.141 x 3.127 mm, 0.4 mm pitch wafer level chip scale package outline H EEE = ) $ EDOO ORFDWLRQ $ * 'HWDLO $ H ( H H $ ' $ $ %RWWRP YLHZ %XPS VLGH 6LGH YLHZ $ E %XPS )URQW YLHZ $ HHH = = E ( FFF GGG $ 2ULHQWDWLRQ UHIHUHQFH =;< = 'HWDLO $ URWDWHG 6HDWLQJ SODQH DDD [ ' 7RS YLHZ :DIHU EDFN VLGH :/&63 B$ =B0(B9 1. Drawing is not to scale. 208/224 Downloaded from Arrow.
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STM32L433xx Package information Table 110. WLCSP49 - 49-ball, 3.141 x 3.127 mm, 0.4 mm pitch wafer level chip scale package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A 0.525 0.555 0.585 0.0207 0.0219 0.0230 A1 - 0.175 - - 0.0069 - A2 - 0.380 - - 0.0150 - - 0.025 - - 0.0010 - b(3) 0.220 0.250 0.280 0.0087 0.0098 0.0110 D 3.106 3.141 3.176 0.1223 0.1237 0.1250 E 3.092 3.127 3.162 0.1217 0.1231 0.1245 e - 0.400 - - 0.
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Package information STM32L433xx Table 111. WLCSP49 recommended PCB design rules (0.4 mm pitch) Dimension Recommended values Pitch 0.4 Dpad 0.225 mm Dsm 0.290 mm typ. (depends on the soldermask registration tolerance) Stencil opening 0.250 mm Stencil thickness 0.100 mm Device marking The following figure gives an example of topside marking orientation versus ball A1 identifier location.
PAGE 211
STM32L433xx 7.7 Package information LQFP48 package information Figure 60. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package outline C ! ! ! 3%!4).' 0,!.% # MM '!5'% 0,!.% CCC # + ! $ $ , , $ 0). )$%.4)&)#!4)/. % % % B E "?-%?6 1. Drawing is not to scale. DocID028794 Rev 4 211/224 219 Downloaded from Arrow.com.
PAGE 212
Package information STM32L433xx Table 112. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A - - 1.600 - - 0.0630 A1 0.050 - 0.150 0.0020 - 0.0059 A2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 D 8.800 9.000 9.200 0.3465 0.3543 0.3622 D1 6.800 7.000 7.200 0.2677 0.2756 0.2835 D3 - 5.500 - - 0.
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STM32L433xx Package information Figure 61. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package recommended footprint AI D 1. Dimensions are expressed in millimeters. Device marking The following figure gives an example of topside marking orientation versus pin 1 identifier location.
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Package information STM32L433xx from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST’s Quality department must be contacted prior to any decision to use these engineering samples to run a qualification activity. 7.8 UFQFPN48 package information Figure 63. UFQFPN48 - 48-lead, 7x7 mm, 0.
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STM32L433xx Package information Table 113. UFQFPN48 - 48-lead, 7x7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A 0.500 0.550 0.600 0.0197 0.0217 0.0236 A1 0.000 0.020 0.050 0.0000 0.0008 0.0020 D 6.900 7.000 7.100 0.2717 0.2756 0.2795 E 6.900 7.000 7.100 0.2717 0.2756 0.2795 D2 5.500 5.600 5.700 0.2165 0.2205 0.2244 E2 5.500 5.600 5.700 0.2165 0.2205 0.2244 L 0.300 0.
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Package information STM32L433xx Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. Figure 65. UFQFPN48 marking (package top view) 670 / 3URGXFW LGHQWLILFDWLRQ &&8 < :: 3LQ LGHQWLILHU 'DWH FRGH $ 5HYLVLRQ FRGH 06Y 9 1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified and therefore not approved for use in production.
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STM32L433xx 7.9 Package information Thermal characteristics The maximum chip junction temperature (TJmax) must never exceed the values given in Table 22: General operating conditions.
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Package information 7.9.2 STM32L433xx Selecting the product temperature range When ordering the microcontroller, the temperature range is specified in the ordering information scheme shown in Section 8: Part numbering. Each temperature range suffix corresponds to a specific guaranteed ambient temperature at maximum dissipation and, to a specific maximum junction temperature.
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STM32L433xx Package information Assuming the following application conditions: Maximum ambient temperature TAmax = 100 °C (measured according to JESD51-2), IDDmax = 20 mA, VDD = 3.5 V, maximum 20 I/Os used at the same time in output at low level with IOL = 8 mA, VOL= 0.4 V PINTmax = 20 mA × 3.5 V= 70 mW PIOmax = 20 × 8 mA × 0.
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Part numbering 8 STM32L433xx Part numbering Table 115.
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STM32L433xx 9 Revision history Revision history Table 116. Document revision history Date Revision 08-Feb-2016 1 Initial release. 2 Updated document title. Updated Table 2: STM32L433xx family device features and peripheral counts. Updated Section 3.15.3: VBAT battery voltage monitoring. Updated Section 3.26: Universal synchronous/asynchronous receiver transmitter (USART). Updated Table 15: STM32L433xx pin definitions. Updated Table 17: Alternate function AF8 to AF15 (for AF0 to AF7 see Table 16).
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Revision history STM32L433xx Table 116. Document revision history (continued) Date 21-Apr-2017 222/224 Downloaded from Arrow.com. Revision Changes 3 (continued) Updated Section 3.9.3: Voltage regulator. Added Table 4: STM32L433xx modes overview. Updated Table 6: STM32L433xx peripherals interconnect matrix. Added Section 3.23.5: Infrared interface (IRTIM). Updated Section 3.26: Universal synchronous/asynchronous receiver transmitter (USART). Updated Figure 5: STM32L433Vx LQFP100 pinout(1).
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STM32L433xx Revision history Table 116. Document revision history (continued) Date 21-Apr-2017 12-Jun-2017 Revision Changes 3 (continued) Added Table 36: Typical current consumption in Run modes, with different codes running from Flash, ART disable and power supplied by external SMPS (VDD12 = 1.10 V). Added Table 36: Typical current consumption in Run modes, with different codes running from Flash, ART disable and power supplied by external SMPS (VDD12 = 1.10 V).
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STM32L433xx IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.