Datasheet

DocID028794 Rev 4 53/224
STM32L433xx Functional overview
55
The CAN peripheral supports:
Supports CAN protocol version 2.0 A, B Active
Bit rates up to 1 Mbit/s
Transmission
Three transmit mailboxes
Configurable transmit priority
Reception
Two receive FIFOs with three stages
14 Scalable filter banks
Identifier list feature
Configurable FIFO overrun
Time-triggered communication option
Disable automatic retransmission mode
16-bit free running timer
Time Stamp sent in last two data bytes
Management
Maskable interrupts
Software-efficient mailbox mapping at a unique address space
3.32 Secure digital input/output and MultiMediaCards Interface
(SDMMC)
The card host interface (SDMMC) provides an interface between the APB peripheral bus
and MultiMediaCards (MMCs), SD memory cards and SDIO cards.
The SDMMC features include the following:
Full compliance with MultiMediaCard System Specification Version 4.2. Card support
for three different databus modes: 1-bit (default), 4-bit and 8-bit
Full compatibility with previous versions of MultiMediaCards (forward compatibility)
Full compliance with SD Memory Card Specifications Version 2.0
Full compliance with SD I/O Card Specification Version 2.0: card support for two
different databus modes: 1-bit (default) and 4-bit
Data transfer up to 48 MHz for the 8 bit mode
Data write and read with DMA capability
3.33 Universal serial bus (USB)
The STM32L433xx devices embed a full-speed USB device peripheral compliant with the
USB specification version 2.0. The internal USB PHY supports USB FS signaling,
embedded DP pull-up and also battery charging detection according to Battery Charging
Specification Revision 1.2. The USB interface implements a full-speed (12
Mbit/s) function
interface with added support for USB 2.0 Link Power Management. It has software-
configurable endpoint setting with packet memory up-to 1
KB and suspend/resume support.
It requires a precise 48
MHz clock which can be generated from the internal main PLL (the
clock source must use a HSE crystal oscillator) or by the internal 48
MHz oscillator in
Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.