Datasheet

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STM32L431xx Pinouts and pin description
77
- - - - - - - 97 C3 PE0 I/O FT - TIM16_CH1, EVENTOUT -
- - - - - - - 98 A2 PE1 I/O FT - EVENTOUT -
32 47 47 A6 A7 63 D4 99 D3 VSS S - - - -
1 48 48 A7 A8 64 E4 100 C4 VDD S - - - -
1. PC13, PC14 and PC15 are supplied through the power switch. Since the switch only sinks a limited amount of current
(3 mA), the use of GPIOs PC13 to PC15 in output mode is limited:
- The speed should not exceed 2 MHz with a maximum load of 30 pF
- These GPIOs must not be used as current sources (e.g. to drive an LED).
2. After a Backup domain power-up, PC13, PC14 and PC15 operate as GPIOs. Their function then depends on the content of
the RTC registers which are not reset by the system reset. For details on how to manage these GPIOs, refer to the Backup
domain and RTC register descriptions in the RM0392 reference manual.
3. After reset, these pins are configured as JTAG/SW debug alternate functions, and the internal pull-up on PA15, PA13, PB4
pins and the internal pull-down on PA14 pin are activated.
Table 14. STM32L431xx pin definitions (continued)
Pin Number
Pin name
(function
after
reset)
Pin type I/O structure Notes
Pin functions
UFQFPN32 LQFP48 UFQFPN48 WLCSP49 WLCSP64 LQFP64 UFBGA64 LQFP100 UFBGA100
Alternate functions
Additional
functions
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