Datasheet
Functional overview STM32L431xx
26/200 DocID028800 Rev 1
3.10 Interconnect matrix
Several peripherals have direct connections between them. This allows autonomous
communication between peripherals, saving CPU resources thus power supply
consumption. In addition, these hardware connections allow fast and predictable latency.
Depending on peripherals, these interconnections can operate in Run, Sleep, low-power run
and sleep, Stop 0, Stop 1 and Stop 2 modes.
Table 5. STM32L431xx peripherals interconnect matrix
Interconnect source
Interconnect
destination
Interconnect action
Run
Sleep
Low-power run
Low-power sleep
Stop 0 / Stop 1
Stop 2
TIMx
TIMx Timers synchronization or chaining Y Y Y Y - -
ADCx
DACx
Conversion triggers Y Y Y Y - -
DMA Memory to memory transfer trigger Y Y Y Y - -
COMPx Comparator output blanking Y Y Y Y - -
TIM15/TIM16 IRTIM Infrared interface output generation Y Y Y Y - -
COMPx
TIM1
TIM2
Timer input channel, trigger, break from
analog signals comparison
YYYY - -
LPTIMERx
Low-power timer triggered by analog
signals comparison
YYYYY
Y
(1)
ADCx TIM1 Timer triggered by analog watchdog Y Y Y Y - -
RTC
TIM16 Timer input channel from RTC events Y Y Y Y - -
LPTIMERx
Low-power timer triggered by RTC alarms
or tampers
YYYYY
Y
(1)
All clocks sources (internal
and external)
TIM2
TIM15, 16
Clock source used as input channel for
RC measurement and trimming
YYYY - -
CSS
CPU (hard fault)
RAM (parity error)
Flash memory (ECC error)
COMPx
PVD
TIM1
TIM15,16
Timer break Y Y Y Y - -
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