Datasheet

Electrical characteristics STM32L431xx
146/200 DocID028800 Rev 1
t
SAMP
Sampling time in sample
and hold mode (code
transition between the
lowest input code and the
highest input code when
DACOUT reaches final
value ±1LSB)
DAC_OUT
pin connected
DAC output buffer
ON, C
SH
= 100 nF
-0.73.5
ms
DAC output buffer
OFF, C
SH
= 100 nF
-10.5 18
DAC_OUT
pin not
connected
(internal
connection
only)
DAC output buffer
OFF
-23.5µs
I
leak
Output leakage current
Sample and hold mode,
DAC_OUT pin connected
-- -
(3)
nA
CI
int
Internal sample and hold
capacitor
- 5.2 7 8.8 pF
t
TRIM
Middle code offset trim
time
DAC output buffer ON 50 - - µs
V
offset
Middle code offset for 1
trim code step
V
REF+
= 3.6 V - 1500 -
µV
V
REF+
= 1.8 V - 750 -
I
DDA
(DAC)
DAC consumption from
V
DDA
DAC output
buffer ON
No load, middle
code (0x800)
- 315 500
µA
No load, worst code
(0xF1C)
- 450 670
DAC output
buffer OFF
No load, middle
code (0x800)
--0.2
Sample and hold mode, C
SH
=
100 nF
-
315 
Ton/(Ton
+Toff)
(4)
670 
Ton/(Ton
+Toff)
(4)
I
DDV
(DAC)
DAC consumption from
V
REF+
DAC output
buffer ON
No load, middle
code (0x800)
- 185 240
µA
No load, worst code
(0xF1C)
- 340 400
DAC output
buffer OFF
No load, middle
code (0x800)
- 155 205
Sample and hold mode, buffer ON,
C
SH
= 100 nF, worst case
-
185 
Ton/(Ton
+Toff)
(4)
400 
Ton/(Ton
+Toff)
(4)
Sample and hold mode, buffer OFF,
C
SH
= 100 nF, worst case
-
155 
Ton/(Ton
+Toff)
(4)
205 
Ton/(Ton
+Toff)
(4)
1. Guaranteed by design.
2. In buffered mode, the output can overshoot above the final value for low input code (starting from min value).
Table 70. DAC characteristics
(1)
(continued)
Symbol Parameter Conditions Min Typ Max Unit
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