Datasheet

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STM32L431xx Electrical characteristics
168
6.3.18 Digital-to-Analog converter characteristics
Table 70. DAC characteristics
(1)
Symbol Parameter Conditions Min Typ Max Unit
V
DDA
Analog supply voltage for
DAC ON
- 1.8 - 3.6
VV
REF+
Positive reference voltage - 1.8 - V
DDA
V
REF-
Negative reference
voltage
-V
SSA
R
L
Resistive load
DAC output
buffer ON
connected to V
SSA
5- -
k
connected to V
DDA
25 - -
R
O
Output Impedance DAC output buffer OFF 9.6 11.7 13.8 k
R
BON
Output impedance sample
and hold mode, output
buffer ON
V
DD
= 2.7 V - - 2
k
V
DD
= 2.0 V - - 3.5
R
BOFF
Output impedance sample
and hold mode, output
buffer OFF
V
DD
= 2.7 V - - 16.5
k
V
DD
= 2.0 V - - 18.0
C
L
Capacitive load
DAC output buffer ON - - 50 pF
C
SH
Sample and hold mode - 0.1 1 µF
V
DAC_OUT
Voltage on DAC_OUT
output
DAC output buffer ON 0.2 -
V
REF+
– 0.2
V
DAC output buffer OFF 0 - V
REF+
t
SETTLING
Settling time (full scale: for
a 12-bit code transition
between the lowest and
the highest input codes
when DAC_OUT reaches
final value ±0.5LSB,
±1 LSB, ±2 LSB, ±4 LSB,
±8 LSB)
Normal mode
DAC output
buffer ON
CL  50 pF,
RL  5 k
±0.5 LSB - 1.7 3
µs
±1 LSB - 1.6 2.9
±2 LSB - 1.55 2.85
±4 LSB - 1.48 2.8
±8 LSB - 1.4 2.75
Normal mode DAC output buffer
OFF, ±1LSB, CL = 10 pF
-22.5
t
WAKEUP
(2)
Wakeup time from off state
(setting the ENx bit in the
DAC Control register) until
final value ±1 LSB
Normal mode DAC output buffer ON
CL  50 pF, RL  5 k
-4.27.5
µs
Normal mode DAC output buffer
OFF, CL  10 pF
-2 5
PSRR V
DDA
supply rejection ratio
Normal mode DAC output buffer ON
CL  50 pF, RL = 5 k, DC
--80-28dB
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