Datasheet

DocID028800 Rev 1 133/200
STM32L431xx Electrical characteristics
168
t
LATR
Trigger conversion
latency Regular and
injected channels without
conversion abort
CKMODE = 00 1.5 2 2.5
1/f
ADC
CKMODE = 01 - - 2.0
CKMODE = 10 - - 2.25
CKMODE = 11 - - 2.125
t
LATRINJ
Trigger conversion
latency Injected channels
aborting a regular
conversion
CKMODE = 00 2.5 3 3.5
1/f
ADC
CKMODE = 01 - - 3.0
CKMODE = 10 - - 3.25
CKMODE = 11 - - 3.125
t
s
Sampling time
f
ADC
= 80 MHz 0.03125 - 8.00625 µs
- 2.5 - 640.5 1/f
ADC
t
ADCVREG_STUP
ADC voltage regulator
start-up time
---20
µs
t
CONV
Total conversion time
(including sampling time)
f
ADC
= 80 MHz
Resolution = 12 bits
0.1875 - 8.1625 µs
Resolution = 12 bits
ts + 12.5 cycles for
successive approximation
= 15 to 653
1/f
ADC
I
DDA
(ADC)
ADC consumption from
the V
DDA
supply
fs = 5 Msps - 730 830
µAfs = 1 Msps - 160 220
fs = 10 ksps - 16 50
I
DDV_S
(ADC)
ADC consumption from
the V
REF+
single ended
mode
fs = 5 Msps - 130 160
µAfs = 1 Msps - 30 40
fs = 10 ksps - 0.6 2
I
DDV_D
(ADC)
ADC consumption from
the V
REF+
differential
mode
fs = 5 Msps - 260 310
µAfs = 1 Msps - 60 70
fs = 10 ksps - 1.3 3
1. Guaranteed by design
2. The I/O analog switch voltage booster is enable when V
DDA
< 2.4 V (BOOSTEN = 1 in the SYSCFG_CFGR1 when
V
DDA
< 2.4V). It is disable when V
DDA
 2.4 V.
3.
V
REF+
can be internally connected to V
DDA
and V
REF-
can be internally connected to V
SSA
, depending on the package.
Refer to Section 4: Pinouts and pin description for further details.
Table 64. ADC characteristics
(1) (2)
(continued)
Symbol Parameter Conditions Min Typ Max Unit
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