Datasheet

Electrical characteristics STM32L431xx
126/200 DocID028800 Rev 1
All I/Os are CMOS- and TTL-compliant (no software configuration required). Their
characteristics cover more than the strict CMOS-technology or TTL parameters. The
coverage of these requirements is shown in
Figure 27 for standard I/Os, and in Figure 27 for
5 V tolerant I/Os.
Figure 27. I/O input characteristics
Output driving current
The GPIOs (general purpose input/outputs) can sink or source up to ±8 mA, and sink or
source up to ± 20
mA (with a relaxed V
OL
/V
OH
).
In the user application, the number of I/O pins which can drive current must be limited to
respect the absolute maximum rating specified in
Section 6.2:
• The sum of the currents sourced by all the I/Os on V
DDIOx,
plus the maximum
consumption of the MCU sourced on V
DD,
cannot exceed the absolute maximum rating
I
VDD
(see Table 18: Voltage characteristics).
• The sum of the currents sunk by all the I/Os on V
SS
, plus the maximum consumption of
the MCU sunk on V
SS
, cannot exceed the absolute maximum rating I
VSS
(see
Table 18: Voltage characteristics).
2. Tested in production.
3. Guaranteed by design.
4. Max(V
DDXXX
) is the maximum value of all the I/O supplies. Refer to Table: Legend/Abbreviations used in the pinout table.
5. All TX_xx IO except FT_u and PC3.
6. This value represents the pad leakage of the IO itself. The total product pad leakage is provided by this formula:
I
To t al _I lea k_ m ax
= 10 µA + [number of IOs where V
IN
is applied on the pad]  I
lkg
(Max).
7. To sustain a voltage higher than MIN(V
DD
, V
DDA
) +0.3 V, the internal Pull-up and Pull-Down resistors must be disabled.
8. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This
PMOS/NMOS contribution to the series resistance is minimal (~10% order).
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