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This is information on a product in full production.

May 2016 DocID028800 Rev 1 1/200

STM32L431xx

Ultra-low-power ARM

Cortex

-M4 32-bit MCU+FPU, 100DMIPS,

up to 256KB Flash, 64KB SRAM, analog, audio

Datasheet - production data

Features

• Ultra-low-power with FlexPowerControl

– 1.71 V to 3.6 V power supply

– -40 °C to 85/105/125 °C temperature range

– 200 nA in V

BAT

mode: supply for RTC and

32x32-bit backup registers

– 8 nA Shutdown mode (5 wakeup pins)

– 28 nA Standby mode (5 wakeup pins)

– 280 nA Standby mode with RTC

– 1.0 µA Stop 2 mode, 1.28 µA Stop 2 with

RTC

– 84 µA/MHz run mode

– Batch acquisition mode (BAM)

– 4 µs wakeup from Stop mode

– Brown out reset (BOR) in all modes except

shutdown

– Interconnect matrix

• Core: ARM

32-bit Cortex

-M4 CPU with FPU,

Adaptive real-time accelerator (ART

Accelerator™) allowing 0-wait-state execution

from Flash memory, frequency up to 80 MHz,

MPU, 100DMIPS/1.25DMIPS/MHz (Dhrystone

2.1), and DSP instructions

• Performance Benchmark

– 1.25 DMIPS/MHz (Drystone 2.1)

– 273.55 Coremark

(3.42 Coremark/MHz @

80 MHz)

• Energy Benchmark

– 176.7 ULPBench

score

• Clock Sources

– 4 to 48 MHz crystal oscillator

– 32 kHz crystal oscillator for RTC (LSE)

– Internal 16 MHz factory-trimmed RC (±1%)

– Internal low-power 32 kHz RC (±5%)

– Internal multispeed 100 kHz to 48 MHz

oscillator, auto-trimmed by LSE (better than

±0.25 % accuracy)

– Internal 48 MHz with clock recovery

– 2 PLLs for system clock, audio, ADC

• RTC with HW calendar, alarms and calibration

• Up to 21 capacitive sensing channels: support

touchkey, linear and rotary touch sensors

• 11x timers: 1x 16-bit advanced motor-control,

1x 32-bit and 2x 16-bit general purpose, 2x 16-

bit basic, 2x low-power 16-bit timers (available

in Stop mode), 2x watchdogs, SysTick timer

• Up to 83 fast I/Os, most 5 V-tolerant

• Memories

– Up to 256 KB single bank Flash,

proprietary code readout protection

– 64 KB of SRAM including 16 KB with

hardware parity check

– Quad SPI memory interface

• Rich analog peripherals (independent supply)

– 1× 12-bit ADC 5 Msps, up to 16-bit with

hardware oversampling, 200 µA/Msps

– 2x 12-bit DAC, low-power sample and hold

– 1x operational amplifier with built-in PGA

– 2x ultra-low-power comparators

• 15x communication interfaces

– 1x SAI (serial audio interface)

–3x I2C FM+(1 Mbit/s), SMBus/PMBus

– 4x USARTs (ISO 7816, LIN, IrDA, modem)

– 3x SPIs (4x SPIs with the Quad SPI)

– CAN (2.0B Active) and SDMMC interface

– SWPMI single wire protocol master I/F

– IRTIM (Infrared interface)

• 14-channel DMA controller

• True random number generator

• CRC calculation unit, 96-bit unique ID

UFBGA100 (7×7)

LQFP64 (10x10)

UFBGA64 (5x5)

LQFP48 (7x7)

LQFP100 (14x14)

WLCSP64

UFQFPN32 (5x5)

WLCSP49UFQFPN48 (7x7)

www.st.com

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Summary of content (200 pages)

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STM32L431xx Ultra-low-power ARM® Cortex®-M4 32-bit MCU+FPU, 100DMIPS, up to 256KB Flash, 64KB SRAM, analog, audio Datasheet - production data Features • Ultra-low-power with FlexPowerControl – 1.71 V to 3.6 V power supply – -40 °C to 85/105/125 °C temperature range – 200 nA in VBAT mode: supply for RTC and 32x32-bit backup registers – 8 nA Shutdown mode (5 wakeup pins) – 28 nA Standby mode (5 wakeup pins) – 280 nA Standby mode with RTC – 1.0 µA Stop 2 mode, 1.
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STM32L431xx • Development support: serial wire debug (SWD), JTAG, Embedded Trace Macrocell™ Table 1. Device summary Reference STM32L431xx 2/200 Downloaded from Arrow.com.
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STM32L431xx Contents Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.1 ARM® Cortex®-M4 core with FPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.
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Contents STM32L431xx 3.17 Voltage reference buffer (VREFBUF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.18 Comparators (COMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.19 Operational amplifier (OPAMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 3.20 Touch sensing controller (TSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 3.21 Random number generator (RNG) . . . . . . . . . . . . . . . . . .
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STM32L431xx 7 Contents 6.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 6.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 6.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 6.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 6.1.5 Pin input voltage . . . . . . . . . . . .
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Contents STM32L431xx 7.1 LQFP100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 7.2 UFBGA100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 7.3 LQFP64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 7.4 UFBGA64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 7.5 WLCSP64 package information . . . . . . . . . . . . . . . . . . . . . . . . . .
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STM32L431xx List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Device summary . . . . . . . . . . . . . . . . . . . . .
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List of tables Table 43. Table 44. Table 45. Table 46. Table 47. Table 48. Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. Table 62. Table 63. Table 64. Table 65. Table 66. Table 67. Table 68. Table 69. Table 70. Table 71. Table 72. Table 73. Table 74. Table 75. Table 76. Table 77. Table 78. Table 79. Table 80. Table 81. Table 82. Table 83. Table 84. Table 85. Table 86. Table 87. Table 88. Table 89. Table 90. Table 91.
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STM32L431xx Table 93. Table 94. Table 95. Table 96. Table 97. Table 98. Table 99. Table 100. Table 101. Table 102. Table 103. Table 104. List of tables package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 UFBGA64 – 64-ball, 5 x 5 mm, 0.5 mm pitch ultra profile fine pitch ball grid array package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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List of figures STM32L431xx List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42. Figure 43.
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STM32L431xx Figure 47. Figure 48. Figure 49. Figure 50. Figure 51. Figure 52. Figure 53. Figure 54. Figure 55. Figure 56. Figure 57. Figure 58. Figure 59. Figure 60. Figure 61. Figure 62. Figure 63. Figure 64. Figure 65. Figure 66. Figure 67. Figure 68. Figure 69. List of figures package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 UFBGA100 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Introduction 1 STM32L431xx Introduction This datasheet provides the ordering information and mechanical device characteristics of the STM32L431xx microcontrollers. This document should be read in conjunction with the STM32L4x1 reference manual (RM0392). The reference manual is available from the STMicroelectronics website www.st.com. For information on the ARM® Cortex®-M4 core, please refer to the Cortex®-M4 Technical Reference Manual, available from the www.arm.com website.
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STM32L431xx 2 Description Description The STM32L431xx devices are the ultra-low-power microcontrollers based on the highperformance ARM® Cortex®-M4 32-bit RISC core operating at a frequency of up to 80 MHz. The Cortex-M4 core features a Floating point unit (FPU) single precision which supports all ARM single-precision data-processing instructions and data types. It also implements a full set of DSP instructions and a memory protection unit (MPU) which enhances application security.
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Description STM32L431xx Table 2. STM32L431xx family device features and peripheral counts (continued) Peripheral Timers Comm.
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STM32L431xx Description Figure 1. STM32L431xx block diagram ' > @ ' > @ &/. &/. &6 1-7567 -7', -7&. 6:&/. 4XDG 63, PHPRU\ LQWHUIDFH -7$* 6: 038 (70 19,& -7'2 6:' -7'2 75$&(&/. ' %86 75$&('> @ $50 &RUWH[ 0 0+] )38 , %86 $57 $&&(/ &$&+( 51* )ODVK XS WR .% $+% EXV PDWUL[ 6 %86 65$0 .% 65$0 .
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Functional overview STM32L431xx 3 Functional overview 3.1 ARM® Cortex®-M4 core with FPU The ARM® Cortex®-M4 with FPU processor is the latest generation of ARM processors for embedded systems. It was developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced response to interrupts.
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STM32L431xx 3.4 Functional overview Embedded Flash memory STM32L431xx devices feature up to 256 Kbyte of embedded Flash memory available for storing programs and data in single bank architecture. The Flash memory contains 128 pages of 2 Kbyte. Flexible protections can be configured thanks to option bytes: • Readout protection (RDP) to protect the whole memory.
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Functional overview STM32L431xx The whole non-volatile memory embeds the error correction code (ECC) feature supporting: 3.5 • single error detection and correction • double error detection. • The address of the ECC fail can be read in the ECC register Embedded SRAM STM32L431xx devices feature 64 Kbyte of embedded SRAM. This SRAM is split into two blocks: • 48 Kbyte mapped at address 0x2000 0000 (SRAM1) • 16 Kbyte located at address 0x1000 0000 with hardware parity check (SRAM2).
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STM32L431xx 3.7 Functional overview Boot modes At startup, BOOT0 pin or nSWBOOT0 option bit, and BOOT1 option bit are used to select one of three boot options: • Boot from user Flash • Boot from system memory • Boot from embedded SRAM BOOT0 value may come from the PH3-BOOT0 pin or from an option bit depending on the value of a user option bit to free the GPIO pad if needed.
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Functional overview STM32L431xx Figure 2. Power supply overview 9''$ GRPDLQ [ $ ' FRQYHUWHU [ FRPSDUDWRUV [ ' $ FRQYHUWHUV [ RSHUDWLRQDO DPSOLILHU 9''$ 966$ 9ROWDJH UHIHUHQFH EXIIHU 9'' GRPDLQ 9'',2 , 2 ULQJ 9&25( GRPDLQ 5HVHW EORFN 7HPS VHQVRU [ 3// +6, 06, +6, 6WDQGE\ FLUFXLWU\ :DNHXS ORJLF ,:'* 966 9'' 9ROWDJH UHJXODWRU /RZ YROWDJH GHWHFWRU &RUH 9&25( 65$0 65$0 'LJLWDO SHULSKHUDOV )ODVK PHPRU\ %DFNXS GRPDLQ /6( FU\VWDO . RVF %.
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STM32L431xx 3.9.3 Functional overview Voltage regulator Two embedded linear voltage regulators supply most of the digital circuitries: the main regulator (MR) and the low-power regulator (LPR). • The MR is used in the Run and Sleep modes and in the Stop 0 mode. • The LPR is used in Low-Power Run, Low-Power Sleep, Stop 1 and Stop 2 modes. It is also used to supply the 16 Kbyte SRAM2 in Standby with RAM2 retention.
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Functional overview STM32L431xx RC, the HSI16 RC and the HSE crystal oscillators are disabled. The LSE or LSI is still running. The RTC can remain active (Stop mode with RTC, Stop mode without RTC). Some peripherals with wakeup capability can enable the HSI16 RC during Stop mode to detect their wakeup condition. Three Stop modes are available: Stop 0, Stop 1 and Stop 2 modes. In Stop 2 mode, most of the VCORE domain is put in a lower leakage mode.
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STM32L431xx Functional overview Table 4.
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Functional overview STM32L431xx Table 4.
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STM32L431xx Functional overview Table 4. Functionalities depending on the working mode(1) (continued) - - - CRC calculation unit O O O O - - - - - - - - - GPIOs O O O O O O O O (9) 5 pins (11) 5 pins - Peripheral Run Sleep Lowpower run Lowpower sleep - (10) Wakeup capability Shutdown Wakeup capability Standby Wakeup capability Stop 2 Wakeup capability Stop 0/1 VBAT (10) 1. Legend: Y = Yes (Enable). O = Optional (Disable by default.
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Functional overview 3.10 STM32L431xx Interconnect matrix Several peripherals have direct connections between them. This allows autonomous communication between peripherals, saving CPU resources thus power supply consumption. In addition, these hardware connections allow fast and predictable latency. Depending on peripherals, these interconnections can operate in Run, Sleep, low-power run and sleep, Stop 0, Stop 1 and Stop 2 modes.
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STM32L431xx Functional overview Sleep Low-power run Low-power sleep Stop 0 / Stop 1 Stop 2 Interconnect source Run Table 5. STM32L431xx peripherals interconnect matrix (continued) TIMx External trigger Y Y Y Y - - LPTIMERx External trigger Y Y Y Y Y (1) ADCx DACx Conversion external trigger Y Y Y Y - - Interconnect destination Interconnect action Y GPIO 1. LPTIM1 only. DocID028800 Rev 1 27/200 48 Downloaded from Arrow.com.
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Functional overview 3.11 STM32L431xx Clocks and startup The clock controller (see Figure 3) distributes the clocks coming from different oscillators to the core and the peripherals. It also manages clock gating for low-power modes and ensures clock robustness. It features: 28/200 Downloaded from Arrow.com.
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STM32L431xx Functional overview interrupt is generated if enabled. LSE failure can also be detected and generated an interrupt. • Clock-out capability: – MCO: microcontroller clock output: it outputs one of the internal clocks for external use by the application – LSCO: low speed clock output: it outputs LSI or LSE in all low-power modes (except VBAT). Several prescalers allow to configure the AHB frequency, the high speed APB (APB2) and the low speed APB (APB1) domains.
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Functional overview STM32L431xx Figure 3. Clock tree WR ,:'* >^/ Z ϯϮ Ŭ,ǌ /6&2 WR 57& 26& B287 >^ K^ ϯϮ͘ϳϲϴ Ŭ,ǌ ͬϯϮ 26& B,1 /6( /6, +6( 0&2 ĺ WR 3:5 6<6&/. +6, 26&B287 ,^ K^ ϰͲϰϴ D,ǌ 26&B,1 WR $+% EXV FRUH PHPRU\ DQG '0$ ůŽĐŬ ƐŽƵƌĐĞ ĐŽŶƚƌŽů +6, , WZ ^ ͬ ϭ͕Ϯ͕͘͘ϱϭϮ +6( ůŽĐŬ ĚĞƚĞĐƚŽƌ +&/. )&/. &RUWH[ IUHH UXQQLQJ FORFN WR &RUWH[ V\VWHP WLPHU ͬ ϴ 06, +6, 6<6&/. W ϭ WZ ^ ͬ ϭ͕Ϯ͕ϰ͕ϴ͕ϭϲ 3&/. WR $3% SHULSKHUDOV ǆϭ Žƌ ǆϮ ,^/ Z ϭϲ D,ǌ /6( +6, 6<6&/.
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STM32L431xx 3.12 Functional overview General-purpose inputs/outputs (GPIOs) Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog alternate functions. Fast I/O toggling can be achieved thanks to their mapping on the AHB2 bus.
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Functional overview STM32L431xx 3.14 Interrupts and events 3.14.1 Nested vectored interrupt controller (NVIC) The devices embed a nested vectored interrupt controller able to manage 16 priority levels, and handle up to 67 maskable interrupt channels plus the 16 interrupt lines of the Cortex®M4.
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STM32L431xx 3.15 Functional overview Analog to digital converter (ADC) The device embeds a successive approximation analog-to-digital converter with the following features: • 12-bit native resolution, with built-in calibration • 5.33 Msps maximum conversion rate with full resolution Down to 18.75 ns sampling time – Increased conversion rate for lower resolution (up to 8.88 Msps for 6-bit resolution) • Up to 16 external channels.
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Functional overview STM32L431xx Table 7. Temperature sensor calibration values 3.15.2 Calibration value name Description Memory address TS_CAL1 TS ADC raw data acquired at a temperature of 30 °C (± 5 °C), VDDA = VREF+ = 3.0 V (± 10 mV) 0x1FFF 75A8 - 0x1FFF 75A9 TS_CAL2 TS ADC raw data acquired at a temperature of 130 °C (± 5 °C), VDDA = VREF+ = 3.
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STM32L431xx Functional overview • Dual DAC channel independent or simultaneous conversions • DMA capability for each channel • External triggers for conversion • Sample and hold low-power mode, with internal or external capacitor The DAC channels are triggered through the timer update outputs that are also connected to different DMA channels. 3.
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Functional overview 3.19 STM32L431xx Operational amplifier (OPAMP) The STM32L431xx embeds one operational amplifier with external or internal follower routing and PGA capability. The operational amplifier features: 3.20 • Low input bias current • Low offset voltage • Low-power mode • Rail-to-rail input Touch sensing controller (TSC) The touch sensing controller provides a simple solution for adding capacitive sensing functionality to any application.
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STM32L431xx 3.22 Functional overview Timers and watchdogs The STM32L431xx includes one advanced control timers, up to five general-purpose timers, two basic timers, two low-power timers, two watchdog timers and a SysTick timer. The table below compares the features of the advanced control, general purpose and basic timers. Table 9.
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Functional overview 3.22.2 STM32L431xx General-purpose timers (TIM2, TIM15, TIM16) There are up to three synchronizable general-purpose timers embedded in the STM32L431xx (see Table 9 for differences). Each general-purpose timer can be used to generate PWM outputs, or act as a simple time base. • TIM2 It is a full-featured general-purpose timer: TIM2 has a 32-bit auto-reload up/downcounter and 32-bit prescaler.
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STM32L431xx Functional overview This low-power timer supports the following features: 3.22.5 • 16-bit up counter with 16-bit autoreload register • 16-bit compare register • Configurable output: pulse, PWM • Continuous/ one shot mode • Selectable software/hardware input trigger • Selectable clock source – Internal clock sources: LSE, LSI, HSI16 or APB clock – External clock source over LPTIM input (working even with no internal clock source running, used by pulse counter application).
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Functional overview 3.23 STM32L431xx Real-time clock (RTC) and backup registers The RTC is an independent BCD timer/counter. It supports the following features: • Calendar with subsecond, seconds, minutes, hours (12 or 24 format), week day, date, month, year, in BCD (binary-coded decimal) format. • Automatic correction for 28, 29 (leap year), 30, and 31 days of the month. • Two programmable alarms. • On-the-fly correction from 1 to 32767 RTC clock pulses.
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STM32L431xx 3.24 Functional overview Inter-integrated circuit interface (I2C) The device embeds 3 I2C. Refer to Table 10: I2C implementation for the features implementation. The I2C bus interface handles communications between the microcontroller and the serial I2C bus. It controls all I2C bus-specific sequencing, protocol, arbitration and timing. The I2C peripheral supports: • • I2C-bus specification and user manual rev.
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Functional overview 3.25 STM32L431xx Universal synchronous/asynchronous receiver transmitter (USART) The STM32L431xx devices have three embedded universal synchronous receiver transmitters (USART1, USART2 and USART3). These interfaces provide asynchronous communication, IrDA SIR ENDEC support, multiprocessor communication mode, single-wire half-duplex communication mode and have LIN Master/Slave capability. They provide hardware management of the CTS and RTS signals, and RS485 Driver Enable.
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STM32L431xx 3.26 Functional overview Low-power universal asynchronous receiver transmitter (LPUART) The device embeds one Low-Power UART. The LPUART supports asynchronous serial communication with minimum power consumption. It supports half duplex single wire communication and modem operations (CTS/RTS). It allows multiprocessor communication. The LPUART has a clock domain independent from the CPU clock, and can wakeup the system from Stop mode using baudrates up to 220 Kbaud.
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Functional overview 3.27 STM32L431xx Serial peripheral interface (SPI) Three SPI interfaces allow communication up to 40 Mbits/s in master and up to 24 Mbits/s slave modes, in half-duplex, full-duplex and simplex modes. The 3-bit prescaler gives 8 master mode frequencies and the frame size is configurable from 4 bits to 16 bits. The SPI interfaces support NSS pulse mode, TI mode and Hardware CRC calculation. All SPI interfaces can be served by the DMA controller. 3.
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STM32L431xx Functional overview Table 12. SAI implementation SAI features Support(1) I2S, LSB or MSB-justified, PCM/DSP, TDM, AC’97 X Mute mode X Stereo/Mono audio frame capability. X 16 slots X Data size configurable: 8-, 10-, 16-, 20-, 24-, 32-bit X FIFO Size X (8 Word) SPDIF X 1. X: supported 3.
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Functional overview • • • • 3.
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STM32L431xx 3.33 Functional overview Quad SPI memory interface (QUADSPI) The Quad SPI is a specialized communication interface targeting single, dual or quad SPI flash memories.
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Functional overview STM32L431xx 3.34 Development support 3.34.1 Serial wire JTAG debug port (SWJ-DP) The ARM SWJ-DP interface is embedded, and is a combined JTAG and serial wire debug port that enables either a serial wire debug or a JTAG probe to be connected to the target.
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STM32L431xx 4 Pinouts and pin description Pinouts and pin description 9'' 966 3( 3( 3% 3% 3+ %227 3% 3% 3% 3% 3% 3' 3' 3' 3' 3' 3' 3' 3' 3& 3& 3& 3$ 3$ Figure 5.
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Pinouts and pin description STM32L431xx Figure 6.
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STM32L431xx Pinouts and pin description Figure 8.
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Pinouts and pin description STM32L431xx 9'' 966 3% 3% 3+ %227 3% 3% 3% 3% 3% 3$ 3$ Figure 11.
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STM32L431xx Pinouts and pin description 966 3+ %227 3% 3% 3% 3% 3% 3$ Figure 13. STM32L431Kx UFQFPN32 pinout(1) 9'' 3$ 3& 26& B,1 3$ 3& 26& B287 3$ 1567 3$ 9''$ 95() 3$ 3$ &.B,1 3$ 3$ 3$ 3$ 9'' 3$ 3$ 3$ 3$ 3$ 3% 3% 966 8)4)31 06Y 9 1. The above figure shows the package top view. Table 13.
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Pinouts and pin description STM32L431xx Table 14.
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STM32L431xx Pinouts and pin description Table 14.
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Pinouts and pin description STM32L431xx Table 14.
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STM32L431xx Pinouts and pin description Table 14.
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Pinouts and pin description STM32L431xx Table 14.
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STM32L431xx Pinouts and pin description Table 14.
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Pinouts and pin description STM32L431xx Table 14.
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STM32L431xx Pinouts and pin description Table 14.
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Pinouts and pin description STM32L431xx Table 14.
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STM32L431xx Pinouts and pin description Table 14.
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Memory mapping 5 STM32L431xx Memory mapping Figure 14.
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STM32L431xx Memory mapping Table 17.
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Memory mapping STM32L431xx Table 17.
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STM32L431xx Memory mapping Table 17. STM32L431xx memory map and peripheral register boundary addresses Bus APB1 Boundary address Size(bytes) Peripheral 0x4000 2C00 - 0x4000 2FFF 1 KB WWDG 0x4000 2800 - 0x4000 2BFF 1 KB RTC 0x4000 1800 - 0x4000 27FF 4 KB Reserved 0x4000 1400 - 0x4000 17FF 1 KB TIM7 0x4000 1000 - 0x4000 13FF 1 KB TIM6 0x4000 0400- 0x4000 0FFF 3 KB Reserved 0x4000 0000 - 0x4000 03FF 1 KB TIM2 1. The gray color is used for reserved boundary addresses.
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Electrical characteristics STM32L431xx 6 Electrical characteristics 6.1 Parameter conditions Unless otherwise specified, all voltages are referenced to VSS. 6.1.1 Minimum and maximum values Unless otherwise specified, the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at TA = 25 °C and TA = TAmax (given by the selected temperature range).
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STM32L431xx 6.1.6 Electrical characteristics Power supply scheme Figure 17. Power supply scheme 9%$7 ĂĐŬƵƉ ĐŝƌĐƵŝƚƌǇ ;>^ ͕ Zd ͕ ĂĐŬƵƉ ƌĞŐŝƐƚĞƌƐͿ ϭ͘ϱϱ ʹ ϯ͘ϲ s WŽǁĞƌ ƐǁŝƚĐŚ 9'' 9&25( Q [ 9'' ZĞŐƵůĂƚŽƌ Khd Q [ Q) *3,2V /E [ ) /HYHO VKLIWHU 9'',2 ,2 ORJLF <ĞƌŶĞů ůŽŐŝĐ ; Wh͕ ŝŐŝƚĂů Θ DĞŵŽƌŝĞƐͿ Q [ 966 9''$ 9''$ 95() ϭϬ Ŷ& ) ϭϬϬ Ŷ& ) 95() 95() $'&V '$&V 23$03V &203V 95()%8) 966$ 06Y 9 Caution: Each power supply pair (VDD/VSS, VDDA/VSSA etc.
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Electrical characteristics 6.1.7 STM32L431xx Current consumption measurement Figure 18. Current consumption measurement scheme ,''B9%$7 9%$7 ,'' 9'' ,''$ 9''$ 06Y 9 6.2 Absolute maximum ratings Stresses above the absolute maximum ratings listed in Table 18: Voltage characteristics, Table 19: Current characteristics and Table 20: Thermal characteristics may cause permanent damage to the device.
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STM32L431xx Electrical characteristics Table 19.
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Electrical characteristics STM32L431xx 6.3 Operating conditions 6.3.1 General operating conditions Table 21. General operating conditions Symbol Parameter Conditions Min Max fHCLK Internal AHB clock frequency - 0 80 fPCLK1 Internal APB1 clock frequency - 0 80 fPCLK2 Internal APB2 clock frequency - 0 80 Standard operating voltage - VDD VDDA Analog supply voltage 1.71 VIN V 3.6 V 1.55 3.6 V TT_xx I/O -0.3 VDDIOx+0.3 All I/O except TT_xx -0.3 MIN(MIN(VDD, VDDA)+3.
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STM32L431xx Electrical characteristics 1. When RESET is released functionality is guaranteed down to VBOR0 Min. 2. This formula has to be applied only on the power supplies related to the IO structure described by the pin definition table. Maximum I/O input voltage is the smallest value between MIN(VDD, VDDA)+3.6 V and 5.5V. 3. For operation with voltage higher than Min (VDD, VDDA) +0.3 V, the internal Pull-up and Pull-Down resistors must be disabled. 4.
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Electrical characteristics STM32L431xx Table 23. Embedded reset and power control block characteristics (continued) Conditions(1) Min Typ Max Rising edge 2.26 2.31 2.36 Falling edge 2.15 2.20 2.25 Rising edge 2.41 2.46 2.51 Falling edge 2.31 2.36 2.41 Rising edge 2.56 2.61 2.66 Falling edge 2.47 2.52 2.57 Rising edge 2.69 2.74 2.79 Falling edge 2.59 2.64 2.69 Rising edge 2.85 2.91 2.96 Falling edge 2.75 2.81 2.86 Rising edge 2.92 2.98 3.04 Falling edge 2.
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STM32L431xx 6.3.4 Electrical characteristics Embedded voltage reference The parameters given in Table 24 are derived from tests performed under the ambient temperature and supply voltage conditions summarized in Table 21: General operating conditions. Table 24. Embedded internal voltage reference Symbol VREFINT Parameter Conditions Internal reference voltage –40 °C < TA < +130 °C Min Typ Max Unit 1.182 1.212 1.
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Electrical characteristics STM32L431xx Figure 19. VREFINT versus temperature 9 0HDQ 86/200 Downloaded from Arrow.com.
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STM32L431xx 6.3.5 Electrical characteristics Supply current characteristics The current consumption is a function of several parameters and factors such as the operating voltage, ambient temperature, I/O pin loading, device software configuration, operating frequencies, I/O pin switching rate, program location in memory and executed binary code. The current consumption is measured as described in Figure 18: Current consumption measurement scheme.
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/200 Downloaded from Arrow.com. DocID028800 Rev 1 - fHCLK = fHSE up to 48MHz included, Supply bypass mode current in PLL ON above Run mode 48 MHz all peripherals disable Parameter 0.2 0.12 8.53 7.7 6.86 5.13 3.46 2.63 1.8 211 117 58.5 30 100 kHz 80 MHz 72 MHz 64 MHz Range 1 48 MHz 32 MHz 24 MHz 16 MHz 2 MHz 1 MHz 400 kHz 100 kHz 0.29 2 MHz 0.81 8 MHz 0.46 1.5 16 MHz 4 MHz 2.37 26 MHz 1. Guaranteed by characterization results, unless otherwise specified. 41.1 70.4 134 230 1.81 2.
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Downloaded from Arrow.com. DocID028800 Rev 1 IDD(Run) 1.05 8 MHz 6.36 4.56 3.45 2.48 310 157 72.6 32.3 Range 1 48 MHz 32 MHz 24 MHz 16 MHz 2 MHz 1 MHz 400 kHz 100 kHz 80 MHz 7.63 100 kHz 7.74 0.12 8.56 1 MHz 64 MHz 0.36 0.23 2 MHz 0.6 1.88 16 MHz 4 MHz 2.66 26 MHz 1. Guaranteed by characterization results, unless otherwise specified. 46 89 173 317 2.51 3.48 4.6 6.4 7.68 7.79 8.61 0.14 0.25 0.37 0.62 1.06 1.9 2.
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/200 Downloaded from Arrow.com. fHCLK = fMSI all peripherals disable FLASH in power-down Supply current in low-power run mode IDD(Run) DocID028800 Rev 1 Range 1 49.2 21.5 100 kHz 2 MHz 400 kHz 205 16 MHz 111 1.82 24 MHz 1 MHz 3.51 2.66 32 MHz 5.19 6.95 64 MHz 48 MHz 7.79 8.63 80 MHz 72 MHz 0.2 0.12 1 MHz 100 kHz 0.29 2 MHz 0.82 8 MHz 0.47 1.54 4 MHz 2.43 2.42 26 MHz 16 MHz 33.3 62.7 126 228 1.84 2.68 3.53 5.22 6.99 7.83 8.68 0.13 0.21 0.3 0.48 0.84 1.
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STM32L431xx Electrical characteristics Table 28. Typical current consumption in Run and Low-power run modes, with different codes running from Flash, ART enable (Cache ON Prefetch OFF) Conditions - IDD(Run) Supply current in Run mode fHCLK = fHSE up to 48 MHz included, bypass mode PLL ON above 48 MHz all peripherals disable Voltage scaling Range 2 fHCLK = 26 MHz Parameter Unit 25 °C 25 °C Reduced code(1) 2.37 91 Coremark 2.69 103 Dhrystone 2.1 2.74 Fibonacci 2.58 99 2.
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Electrical characteristics STM32L431xx Table 29.
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Downloaded from Arrow.com. DocID028800 Rev 1 IDD(Sleep) 0.11 2.23 2.02 1.82 1.34 0.93 0.73 0.53 71.8 45.0 27.0 22.8 72 MHz 64 MHz Range 1 48 MHz 32 MHz 24 MHz 16 MHz 2 MHz 1 MHz 400 kHz 100 kHz 0.13 1 MHz 80 MHz 0.16 2 MHz 8 MHz 0.20 0.46 0.29 16 MHz 4 MHz 0.68 26 MHz 30.9 40.7 57.3 80.7 0.55 0.75 0.95 1.36 1.84 2.04 2.25 0.13 0.15 0.17 0.21 0.30 0.48 0.69 25 °C 55 °C fHCLK 100 kHz Range 2 Voltage scaling 1.
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/200 Downloaded from Arrow.com. Supply current in low-power sleep mode IDD(LPSleep ) Voltage scaling fHCLK = fMSI all peripherals disable 58.7 39.4 20.8 14.3 2 MHz 1 MHz 400 kHz 100 kHz Supply current in Stop 2 mode, RTC disabled Supply current in RTC clocked by LSE Stop 2 mode, bypassed at 32768 Hz RTC enabled IDD (Stop 2) IDD (Stop 2 with RTC) Conditions Parameter Symbol DocID028800 Rev 1 RTC clocked by LSE quartz(2) in low drive mode RTC clocked by LSI - - 55.1 62.1 79.3 103.
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Downloaded from Arrow.com. Supply current during wakeup from Stop 2 mode Parameter 3V 3V 3V Wakeup clock is MSI = 4 MHz, voltage Range 2. See (3). Wakeup clock is HSI16 = 16 MHz, voltage Range 1. See (3). VDD Wakeup clock is MSI = 48 MHz, voltage Range 1. See (3). - Conditions 1.54 1.52 1.85 - - - 85 °C TYP - - - - - - - - - 105 °C 125 °C 25 °C - - - 55 °C 3. Wakeup with code execution from Flash.
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/200 Downloaded from Arrow.com. Parameter RTC clocked by LSI - - Conditions DocID028800 Rev 1 1.22 1.20 3V 3V 1.14 12.4 - - - 13 12.6 12.4 12.3 16.1 13.6 13 12.8 13.4 13 12.8 12.7 12.9 12.6 12.5 43.6 - - - 44.8 44.1 43.8 43.7 48.8 45.4 44.4 44 45.3 44.6 44.2 43.9 44.8 44.1 43.8 - - - 101 99.6 99.3 99.1 103 99.1 97.6 96.9 99.5 98.1 97.4 96.8 98.9 97.7 97 96.
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Downloaded from Arrow.com. Parameter 108 110 111 114 1.8 V 2.4 V 3V 3.6 V 2. Guaranteed by test in production. 125 123 121 119 25 °C 55 °C VDD Conditions 1. Guaranteed by characterization results, unless otherwise specified. Supply current in IDD (Stop 0) Stop 0 mode, RTC disabled Symbol 163 161 160 158 85 °C TYP 227 224 223 221 355 352 349 347 142 139 136 133 105 °C 125 °C 25 °C Table 35.
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/200 Downloaded from Arrow.com. Parameter Supply current in Standby IDD(Standby mode (backup with RTC) registers retained), RTC enabled Supply current in Standby mode (backup IDD(Standby) registers retained), RTC disabled Symbol DocID028800 Rev 1 27.7 50.9 90.2 253 216 342 416 1.8 V 2.4 V 3V 3.6 V 1.8 V 2.4 V 3V - 386 513 771 342 521 2.4 V 3V 3.6 V 1.8 V 2.4 V - 219 364 142 249 1.8 V 2.4 V 548 715 281 388 535 836 1.8 V 2.4 V RTC clocked by LSE quartz (3) in low drive mode 3 V 3.
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Downloaded from Arrow.com. Parameter Wakeup clock is MSI = 4 MHz. See (5). - - Conditions 178 184 3V 3.
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/200 Downloaded from Arrow.com. Parameter Supply current during wakeup from Shutdown mode Wakeup clock is MSI = 4 MHz. See (3).
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Downloaded from Arrow.com. RTC disabled - Conditions RTC enabled and clocked by LSE quartz(2) RTC enabled and Backup domain clocked by LSE supply current bypassed at 32768 Hz Parameter 345 455 591 3V 3.6 V 256 1.8 V 2.4 V 419 3.6 V 154 1.8 V 316 6 3.6 V 228 5 3V 3V 1 2.4 V 2.
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Electrical characteristics STM32L431xx I/O system current consumption The current consumption of the I/O system has two components: static and dynamic. I/O static current consumption All the I/Os used as inputs with pull-up generate current consumption when the pin is externally held low. The value of this current consumption can be simply computed by using the pull-up/pull-down resistors values given in Table 59: I/O static characteristics.
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STM32L431xx Electrical characteristics On-chip peripheral current consumption The current consumption of the on-chip peripherals is given in Table 39.
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Electrical characteristics STM32L431xx Table 39. Peripheral current consumption (continued) Range 1 Range 2 Low-power run and sleep RTCA 1.7 1.1 2.1 CRS 0.3 0.3 0.6 I2C1 independent clock domain 3.5 2.8 3.4 I2C1 clock domain 1.1 0.9 1.0 I2C2 independent clock domain 3.5 3.0 3.4 I2C2 clock domain 1.1 0.7 0.9 I2C3 independent clock domain 2.9 2.3 2.5 I2C3 clock domain 0.9 0.4 0.8 LPUART1 independent clock domain 1.9 1.6 1.8 LPUART1 clock domain 0.6 0.6 0.
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STM32L431xx Electrical characteristics Table 39. Peripheral current consumption (continued) Range 1 Range 2 Low-power run and sleep FW 0.2 0.2 0.2 SAI1 independent clock domain 2.3 1.8 1.9 SAI1 clock domain 2.1 1.8 2.0 SDMMC1 independent clock domain 4.7 3.9 3.9 SDMMC1 clock domain 2.5 1.9 1.9 SPI1 1.8 1.6 1.7 SYSCFG/VREFBUF/COMP 0.6 0.5 0.6 TIM1 8.1 6.5 7.6 TIM15 3.7 3.0 3.4 TIM16 2.7 2.1 2.6 USART1 independent clock domain 4.8 4.2 4.6 USART1 clock domain 1.
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Electrical characteristics STM32L431xx Table 40.
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STM32L431xx Electrical characteristics Table 40. Low-power mode wakeup timings(1) (continued) Symbol Parameter Conditions Typ Max Wakeup clock MSI = 48 MHz 8.02 9.24 Wakeup clock HSI16 = 16 MHz 7.66 8.95 Wakeup clock MSI = 24 MHz 8.5 9.54 Wakeup clock HSI16 = 16 MHz 7.75 8.95 Wakeup clock MSI = 4 MHz 12.06 13.16 Wakeup clock MSI = 48 MHz 5.45 6.79 Wakeup clock HSI16 = 16 MHz 6.9 7.98 Wakeup clock MSI = 24 MHz 6.3 7.36 Wakeup clock HSI16 = 16 MHz 6.9 7.
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Electrical characteristics 6.3.7 STM32L431xx External clock source characteristics High-speed external user clock generated from an external source In bypass mode the HSE oscillator is switched off and the input pin is a standard GPIO. The external clock signal has to respect the I/O characteristics in Section 6.3.14. However, the recommended clock input waveform is shown in Figure 20: High-speed external clock source AC timing diagram. Table 43.
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STM32L431xx Electrical characteristics Low-speed external user clock generated from an external source In bypass mode the LSE oscillator is switched off and the input pin is a standard GPIO. The external clock signal has to respect the I/O characteristics in Section 6.3.14. However, the recommended clock input waveform is shown in Figure 21. Table 44.
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Electrical characteristics STM32L431xx High-speed external clock generated from a crystal/ceramic resonator The high-speed external (HSE) clock can be supplied with a 4 to 48 MHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on design simulation results obtained with typical external components specified in Table 45.
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STM32L431xx Note: Electrical characteristics For information on selecting the crystal, refer to the application note AN2867 “Oscillator design guide for ST microcontrollers” available from the ST website www.st.com. Figure 22. Typical application with an 8 MHz crystal 5HVRQDWRU ZLWK LQWHJUDWHG FDSDFLWRUV &/ 26&B,1 0+] UHVRQDWRU &/ 5(;7 I+6( 5) %LDV FRQWUROOHG JDLQ 26&B287 06 9 1. REXT value depends on the crystal characteristics.
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Electrical characteristics STM32L431xx 1. Guaranteed by design. 2. Refer to the note and caution paragraphs below the table, and to the application note AN2867 “Oscillator design guide for ST microcontrollers”. 3. tSU(LSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 kHz oscillation is reached.
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STM32L431xx 6.3.8 Electrical characteristics Internal clock source characteristics The parameters given in Table 47 are derived from tests performed under ambient temperature and supply voltage conditions summarized in Table 21: General operating conditions. The provided curves are characterization results, not tested in production. High-speed internal (HSI16) RC oscillator Table 47.
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Electrical characteristics STM32L431xx Figure 24. HSI16 frequency versus temperature 0+] PLQ PHDQ & PD[ 06Y 9 114/200 Downloaded from Arrow.com.
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STM32L431xx Electrical characteristics Multi-speed internal (MSI) RC oscillator Table 48. MSI oscillator characteristics(1) Symbol Parameter Conditions Min Typ Max Range 0 98.7 100 101.3 Range 1 197.4 200 202.6 Range 2 394.8 400 405.2 Range 3 789.6 800 810.4 Range 4 0.987 1 1.013 Range 5 1.974 2 2.026 Range 6 3.948 4 4.052 Range 7 7.896 8 8.104 Range 8 15.79 16 16.21 Range 9 23.69 24 24.31 Range 10 31.58 32 32.42 Range 11 47.38 48 48.62 Range 0 - 98.
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Electrical characteristics STM32L431xx Table 48. MSI oscillator characteristics(1) (continued) Symbol Parameter Conditions Min Typ VDD=1.62 V to 3.6 V -1.2 - VDD=2.4 V to 3.6 V -0.5 - VDD=1.62 V to 3.6 V -2.5 - VDD=2.4 V to 3.6 V -0.8 - VDD=1.62 V to 3.6 V -5 - VDD=2.4 V to 3.6 V -1.
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STM32L431xx Electrical characteristics Table 48. MSI oscillator characteristics(1) (continued) Symbol IDD(MSI)(4) Parameter MSI oscillator power consumption Conditions MSI and PLL mode Min Typ Max Range 0 - - 0.6 1 Range 1 - - 0.8 1.2 Range 2 - - 1.2 1.7 Range 3 - - 1.9 2.5 Range 4 - - 4.7 6 Range 5 - - 6.5 9 Range 6 - - 11 15 Range 7 - - 18.5 25 Range 8 - - 62 80 Range 9 - - 85 110 Range 10 - - 110 130 Range 11 - - 155 190 Unit µA 1.
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Electrical characteristics STM32L431xx High-speed internal 48 MHz (HSI48) RC oscillator Table 49. HSI48 oscillator characteristics(1) Symbol fHSI48 TRIM USER TRIM COVERAGE Parameter Conditions HSI48 Frequency VDD=3.
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STM32L431xx Electrical characteristics Figure 26. HSI48 frequency versus temperature $YJ PLQ & PD[ 06Y 9 Low-speed internal (LSI) RC oscillator Table 50. LSI oscillator characteristics(1) Symbol Parameter LSI Frequency fLSI Min Typ Max VDD = 3.0 V, TA = 30 °C 31.04 - 32.96 VDD = 1.62 to 3.6 V, TA = -40 to 125 °C 29.
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Electrical characteristics STM32L431xx Table 51. PLL, PLLSAI1 characteristics(1) (continued) Symbol Parameter fPLL_P_OUT PLL multiplier output clock P fPLL_Q_OUT PLL multiplier output clock Q fPLL_R_OUT PLL multiplier output clock R fVCO_OUT tLOCK Jitter IDD(PLL) PLL VCO output PLL lock time RMS cycle-to-cycle jitter RMS period jitter PLL power consumption on VDD(1) Conditions Min Typ Max Voltage scaling Range 1 3.0968 - 80 Voltage scaling Range 2 3.
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STM32L431xx 6.3.10 Electrical characteristics Flash memory characteristics Table 52. Flash memory characteristics(1) Symbol Parameter Conditions Typ Max Unit tprog 64-bit programming time - 81.69 90.76 µs tprog_row one row (32 double word) programming time normal programming 2.61 2.90 fast programming 1.91 2.12 tprog_page one page (2 Kbyte) programming time normal programming 20.91 23.24 fast programming 15.29 16.98 22.02 24.47 normal programming 5.35 5.
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Electrical characteristics 6.3.11 STM32L431xx EMC characteristics Susceptibility tests are performed on a sample basis during device characterization. Functional EMS (electromagnetic susceptibility) While a simple application is executed on the device (toggling 2 LEDs through I/O ports). the device is stressed by two electromagnetic events until a failure occurs.
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STM32L431xx Electrical characteristics Prequalification trials Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1 second. To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015).
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Electrical characteristics STM32L431xx Static latch-up Two complementary static tests are required on six parts to assess the latch-up performance: • A supply overvoltage is applied to each power supply pin. • A current injection is applied to each input, output and configurable I/O pin. These tests are compliant with EIA/JESD 78A IC latch-up standard. Table 57. Electrical sensitivities Symbol LU 6.3.
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STM32L431xx 6.3.14 Electrical characteristics I/O port characteristics General input/output characteristics Unless otherwise specified, the parameters given in Table 59 are derived from tests performed under the conditions summarized in Table 21: General operating conditions. All I/Os are designed as CMOS- and TTL-compliant. Table 59. I/O static characteristics Symbol VIL(1) VIH(1) Vhys(3) Parameter Conditions Min Typ Max Unit I/O input low level voltage 1.62 V
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Electrical characteristics STM32L431xx 2. Tested in production. 3. Guaranteed by design. 4. Max(VDDXXX) is the maximum value of all the I/O supplies. Refer to Table: Legend/Abbreviations used in the pinout table. 5. All TX_xx IO except FT_u and PC3. 6. This value represents the pad leakage of the IO itself. The total product pad leakage is provided by this formula: ITotal_Ileak_max = 10 µA + [number of IOs where VIN is applied on the pad] ₓ Ilkg(Max). 7. To sustain a voltage higher than MIN(VDD, VDDA) +0.
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STM32L431xx Electrical characteristics Output voltage levels Unless otherwise specified, the parameters given in the table below are derived from tests performed under the ambient temperature and supply voltage conditions summarized in Table 21: General operating conditions. All I/Os are CMOS- and TTL-compliant (FT OR TT unless otherwise specified). Table 60. Output voltage characteristics(1) Symbol VOL VOH Parameter Conditions Min Max - 0.4 VDDIOx-0.4 - - 0.4 2.4 - - 1.3 VDDIOx-1.
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Electrical characteristics STM32L431xx Table 61. I/O AC characteristics(1)(2) Speed Symbol Fmax Parameter Maximum frequency 00 Tr/Tf Fmax Output rise and fall time Maximum frequency 01 Tr/Tf 128/200 Downloaded from Arrow.com. Output rise and fall time Conditions Min Max C=50 pF, 2.7 V≤VDDIOx≤3.6 V - 5 C=50 pF, 1.62 V≤VDDIOx≤2.7 V - 1 C=50 pF, 1.08 V≤VDDIOx≤1.62 V - 0.1 C=10 pF, 2.7 V≤VDDIOx≤3.6 V - 10 C=10 pF, 1.62 V≤VDDIOx≤2.7 V - 1.5 C=10 pF, 1.08 V≤VDDIOx≤1.62 V - 0.
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STM32L431xx Electrical characteristics Table 61. I/O AC characteristics(1)(2) (continued) Speed Symbol Fmax Parameter Maximum frequency 10 Tr/Tf Fmax Output rise and fall time Maximum frequency 11 Tr/Tf Fm+ Fmax Tf Output rise and fall time Maximum frequency (4) Output fall time Conditions Min Max C=50 pF, 2.7 V≤VDDIOx≤3.6 V - 50 C=50 pF, 1.62 V≤VDDIOx≤2.7 V - 25 C=50 pF, 1.08 V≤VDDIOx≤1.62 V - 5 C=10 pF, 2.7 V≤VDDIOx≤3.6 V - 100(3) C=10 pF, 1.62 V≤VDDIOx≤2.7 V - 37.
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Electrical characteristics STM32L431xx Figure 28. I/O AC characteristics definition(1) W I ,2 RXW W U ,2 RXW 7 0D[LPXP IUHTXHQF\ LV DFKLHYHG LI W W U I 7 DQG LI WKH GXW\ F\FOH LV ZKHQ ORDGHG E\ WKH VSHFLILHG FDSDFLWDQFH 06 9 1. Refer to Table 61: I/O AC characteristics. 6.3.15 NRST pin characteristics The NRST pin input driver uses the CMOS technology. It is connected to a permanent pullup resistor, RPU.
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STM32L431xx Electrical characteristics Figure 29. Recommended NRST pin protection ([WHUQDO UHVHW FLUFXLW 9'' 1567 538 ,QWHUQDO UHVHW )LOWHU ) 06 9 1. The reset network protects the device against parasitic resets. 2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in Table 62: NRST pin characteristics. Otherwise the reset will not be taken into account by the device. 3.
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Electrical characteristics 6.3.17 STM32L431xx Analog-to-Digital converter characteristics Unless otherwise specified, the parameters given in Table 64 are preliminary values derived from tests performed under ambient temperature, fPCLK frequency and VDDA supply voltage conditions summarized in Table 21: General operating conditions. Note: It is recommended to perform a calibration after each power-up. Table 64.
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STM32L431xx Electrical characteristics Table 64. ADC characteristics(1) (2) (continued) Symbol Parameter tLATR Trigger conversion latency Regular and injected channels without conversion abort tLATRINJ ts Conditions Min Typ Max CKMODE = 00 1.5 2 2.5 CKMODE = 01 - - 2.0 CKMODE = 10 - - 2.25 CKMODE = 11 - - 2.125 2.5 3 3.5 - - 3.0 - - 3.25 - - 3.125 0.03125 - 8.00625 µs - 2.5 - 640.5 1/fADC - - - 20 µs 0.1875 - 8.
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Electrical characteristics STM32L431xx Equation 1: RAIN max formula TS - – R ADC R AIN < --------------------------------------------------------------N+2 f ADC × C ADC × ln ( 2 ) The formula above (Equation 1) is used to determine the maximum external impedance allowed for an error below 1/4 of LSB. Here N = 12 (from 12-bit resolution). Table 65. Maximum ADC RAIN(1)(2) Resolution 12 bits 10 bits 8 bits 134/200 Downloaded from Arrow.com. Sampling cycle @80 MHz Sampling time [ns] @80 MHz 2.
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STM32L431xx Electrical characteristics Table 65. Maximum ADC RAIN(1)(2) (continued) Resolution 6 bits Sampling cycle @80 MHz Sampling time [ns] @80 MHz 2.5 RAIN max (Ω) Fast channels(3) Slow channels(4) 31.25 220 N/A 6.5 81.25 560 330 12.5 156.25 1200 1000 24.5 306.25 2700 2200 47.5 593.75 3900 3300 92.5 1156.25 8200 6800 247.5 3093.75 18000 15000 640.5 8006.75 50000 50000 1. Guaranteed by design. 2. The I/O analog switch voltage booster is enable when VDDA < 2.
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Electrical characteristics STM32L431xx Table 66. ADC accuracy - limited test conditions 1(1)(2)(3) Symbol Parameter ET Total unadjusted error EO Conditions(4) Single ended Differential Single ended Offset error Differential Single ended EG Gain error Differential ED EL Differential linearity ADC clock frequency ≤ error 80 MHz, Sampling rate ≤ 5.
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STM32L431xx Electrical characteristics Table 66. ADC accuracy - limited test conditions 1(1)(2)(3) (continued) Symbol THD Conditions(4) Parameter Total harmonic distortion ADC clock frequency ≤ Single 80 MHz, ended Sampling rate ≤ 5.33 Msps, VDDA = VREF+ = 3 V, Differential TA = 25 °C Min Typ Max Unit Fast channel (max speed) - -74 -73 Slow channel (max speed) - -74 -73 Fast channel (max speed) - -79 -76 Slow channel (max speed) - -79 -76 dB 1. Guaranteed by design. 2.
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Electrical characteristics STM32L431xx Table 67. ADC accuracy - limited test conditions 2(1)(2)(3) Symbol Parameter ET Total unadjusted error EO Conditions(4) Single ended Differential Single ended Offset error Differential Single ended EG Gain error Differential ED EL Differential linearity error ADC clock frequency ≤ 80 MHz, Sampling rate ≤ 5.
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STM32L431xx Electrical characteristics Table 67. ADC accuracy - limited test conditions 2(1)(2)(3) (continued) Symbol THD Conditions(4) Parameter Total harmonic distortion Fast channel (max speed) Single ADC clock frequency ≤ ended Slow channel (max speed) 80 MHz, Sampling rate ≤ 5.33 Msps, Fast channel (max speed) Differential 2 V ≤ VDDA Slow channel (max speed) Min Typ Max Unit - -74 -65 - -74 -67 - -79 -70 - -79 -71 dB 1. Guaranteed by design. 2.
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Electrical characteristics STM32L431xx Table 68. ADC accuracy - limited test conditions 3(1)(2)(3) Symbol Parameter ET Total unadjusted error EO Conditions(4) Single ended Differential Single ended Offset error Differential Single ended EG Gain error Differential ED EL Differential linearity ADC clock frequency ≤ error 80 MHz, Sampling rate ≤ 5.33 Msps, 1.65 V ≤ VDDA = VREF+ ≤ 3.
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STM32L431xx Electrical characteristics Table 68. ADC accuracy - limited test conditions 3(1)(2)(3) (continued) Symbol THD Conditions(4) Parameter Total harmonic distortion ADC clock frequency ≤ Single 80 MHz, ended Sampling rate ≤ 5.33 Msps, 1.65 V ≤ VDDA = VREF+ ≤ Differential 3.6 V, Voltage scaling Range 1 Min Typ Max Unit Fast channel (max speed) - -69 -67 Slow channel (max speed) - -71 -67 Fast channel (max speed) - -72 -71 Slow channel (max speed) - -72 -71 dB 1.
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Electrical characteristics STM32L431xx Table 69. ADC accuracy - limited test conditions 4(1)(2)(3) Symbol Parameter ET Total unadjusted error EO Conditions(4) Single ended Differential Single ended Offset error Differential Single ended EG Gain error Differential ED EL Differential linearity ADC clock frequency ≤ error 26 MHz, 1.65 V ≤ VDDA = VREF+ ≤ 3.
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STM32L431xx Electrical characteristics Table 69. ADC accuracy - limited test conditions 4(1)(2)(3) (continued) Symbol THD Conditions(4) Parameter ADC clock frequency ≤ 26 MHz, 1.65 V ≤ VDDA = VREF+ ≤ 3.6 V, Voltage scaling Range 2 Total harmonic distortion Single ended Differential Min Typ Max Unit Fast channel (max speed) - -71 -69 Slow channel (max speed) - -71 -69 Fast channel (max speed) - -73 -72 Slow channel (max speed) - -73 -72 dB 1. Guaranteed by design. 2.
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Electrical characteristics STM32L431xx Figure 31. Typical connection diagram using the ADC 9''$ 97 5$,1 9$,1 6DPSOH DQG KROG $'& FRQYHUWHU 5$'& $,1[ &SDUDVLWLF 97 ,ONJ ELW FRQYHUWHU &$'& 06 9 1. Refer to Table 64: ADC characteristics for the values of RAIN, RADC and CADC. 2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad capacitance (refer to Table 59: I/O static characteristics for the value of the pad capacitance).
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STM32L431xx 6.3.18 Electrical characteristics Digital-to-Analog converter characteristics Table 70. DAC characteristics(1) Symbol Parameter Conditions Min Typ Max VDDA Analog supply voltage for DAC ON - 1.8 - 3.6 VREF+ Positive reference voltage - 1.8 - VDDA VREF- Negative reference voltage 5 - - connected to VDDA 25 - - 9.6 11.7 13.
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Electrical characteristics STM32L431xx Table 70.
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STM32L431xx Electrical characteristics 3. Refer to Table 59: I/O static characteristics. 4. Ton is the Refresh phase duration. Toff is the Hold phase duration. Refer to RM0392 reference manual for more details. Figure 32. 12-bit buffered / non-buffered DAC %XIIHUHG QRQ EXIIHUHG '$& %XIIHU 5/2$' ELW GLJLWDO WR DQDORJ FRQYHUWHU '$&[B287 &/2$' DL G 1.
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Electrical characteristics STM32L431xx Table 71. DAC accuracy(1) (continued) Symbol Gain TUE TUECal SNR THD SINAD ENOB Parameter Gain error(5) Total unadjusted error Total unadjusted error after calibration Signal-to-noise ratio Total harmonic distortion Signal-to-noise and distortion ratio Effective number of bits Conditions Min Typ Max DAC output buffer ON CL ≤ 50 pF, RL ≥ 5 kΩ - - ±0.5 DAC output buffer OFF CL ≤ 50 pF, no RL - - ±0.
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STM32L431xx 6.3.19 Electrical characteristics Voltage reference buffer characteristics Table 72. VREFBUF characteristics(1) Symbol Parameter Conditions Normal mode VDDA VREFBUF_ OUT Analog supply voltage Voltage reference output Degraded mode(2) Normal mode Degraded mode(2) Min Typ Max VRS = 0 2.4 - 3.6 VRS = 1 2.8 - 3.6 VRS = 0 1.65 - 2.4 VRS = 1 1.65 - 2.8 2.048 2.049(3) (3) VRS = 0 2.046 VRS = 1 2.498(3) 2.5 2.
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Electrical characteristics STM32L431xx Table 72. VREFBUF characteristics(1) (continued) Symbol Parameter VREFBUF IDDA(VREF consumption BUF) from VDDA Conditions Min Typ Max Iload = 0 µA - 16 25 Iload = 500 µA - 18 30 Iload = 4 mA - 35 50 Unit µA 1. Guaranteed by design, unless otherwise specified. 2. In degraded mode, the voltage reference buffer can not maintain accurately the output voltage which will follow (VDDA drop voltage). 3. Guaranteed by test in production. 4.
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STM32L431xx 6.3.20 Electrical characteristics Comparator characteristics Table 73. COMP characteristics(1) Symbol Conditions Min Typ Max Analog supply voltage - 1.62 - 3.6 Comparator input voltage range - 0 - VDDA V VBG(2) Scaler input voltage - VSC Scaler offset voltage - VDDA VIN IDDA(SCALER) Parameter VREFINT - ±5 ±10 mV BRG_EN=0 (bridge disable) - 200 300 nA BRG_EN=1 (bridge enable) - 0.8 1 µA - 100 200 µs VDDA ≥ 2.7 V - - 5 VDDA < 2.
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Electrical characteristics STM32L431xx 2. Refer to Table 24: Embedded internal voltage reference. 3. Guaranteed by characterization results. 6.3.21 Operational amplifiers characteristics Table 74. OPAMP characteristics(1) Symbol Parameter Conditions Min Typ Max Unit VDDA Analog supply voltage(2) - 1.8 - 3.6 V CMIR Common mode input range - 0 - VDDA V 25 °C, No Load on output. - - ±1.5 All voltage/Temp. - - ±3 Normal mode - ±5 - Low-power mode - ±10 - - 0.8 1.
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STM32L431xx Electrical characteristics Table 74.
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Electrical characteristics STM32L431xx Table 74.
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STM32L431xx 6.3.22 Electrical characteristics Temperature sensor characteristics Table 75. TS characteristics Symbol Parameter TL(1) Min Typ Max Unit - ±1 ±2 °C 2.3 2.5 2.7 mV/°C 0.742 0.76 0.
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Electrical characteristics STM32L431xx Table 78. TIMx(1) characteristics Symbol tres(TIM) Parameter Timer resolution time Conditions Min Max Unit - 1 - tTIMxCLK fTIMxCLK = 80 MHz 12.5 - ns 0 fTIMxCLK/2 MHz 0 40 MHz TIMx (except TIM2) - 16 TIM2 - 32 - 1 65536 tTIMxCLK fTIMxCLK = 80 MHz 0.0125 819.2 µs - - 65536 × 65536 tTIMxCLK fTIMxCLK = 80 MHz - 53.
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STM32L431xx 6.3.25 Electrical characteristics Communication interfaces characteristics I2C interface characteristics The I2C interface meets the timings requirements of the I2C-bus specification and user manual rev. 03 for: • Standard-mode (Sm): with a bit rate up to 100 kbit/s • Fast-mode (Fm): with a bit rate up to 400 kbit/s • Fast-mode Plus (Fm+): with a bit rate up to 1 Mbit/s.
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Electrical characteristics STM32L431xx SPI characteristics Unless otherwise specified, the parameters given in Table 82 for SPI are derived from tests performed under the ambient temperature, fPCLKx frequency and supply voltage conditions summarized in Table 21: General operating conditions. • Output speed is set to OSPEEDRy[1:0] = 11 • Capacitive load C = 30 pF • Measurement points are done at CMOS levels: 0.5 ₓ VDD Refer to Section 6.3.
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STM32L431xx Electrical characteristics Table 82. SPI characteristics(1) (continued) Symbol tv(SO) Parameter Data output valid time tv(MO) th(SO) th(MO) Conditions Data output hold time Min Typ Max Slave mode 2.7 < VDD < 3.6 V Voltage Range 1 - 12.5 13.5 Slave mode 1.71 < VDD < 3.6 V Voltage Range 1 - 12.5 24 Slave mode 1.71 < VDD < 3.6 V Voltage Range 2 - 12.5 33 Master mode - 4.5 6 Slave mode 7 - - Master mode 0 - - Unit ns ns 1.
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Electrical characteristics STM32L431xx Figure 34. SPI timing diagram - slave mode and CPHA = 1 166 LQSXW 6&. LQSXW W68 166 &3+$ &32/ &3+$ &32/ WK 166 WF 6&. WZ 6&.+ WZ 6&./ WK 62 WY 62 WD 62 0,62 287387 06% 287 WGLV 62 /6% 287 WK 6, WVX 6, 026, ,1387 %,7 287 WU 6&. WI 6&. 06% ,1 %,7 ,1 /6% ,1 DL E 1. Measurement points are done at CMOS levels: 0.3 VDD and 0.7 VDD. Figure 35. SPI timing diagram - master mode +LJK 166 LQSXW 6&. 2XWSXW &3+$ &32/ 6&. 2XWSXW WF 6&.
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STM32L431xx Electrical characteristics Quad SPI characteristics Unless otherwise specified, the parameters given in Table 83 and Table 84 for Quad SPI are derived from tests performed under the ambient temperature, fAHB frequency and VDD supply voltage conditions summarized in Table 21: General operating conditions, with the following configuration: • Output speed is set to OSPEEDRy[1:0] = 11 • Capacitive load C = 15 or 20 pF • Measurement points are done at CMOS levels: 0.5 ₓ VDD Refer to Section 6.3.
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Electrical characteristics STM32L431xx Table 84. QUADSPI characteristics in DDR mode(1) Symbol FCK 1/t(CK) tw(CKH) tw(CKL) Parameter Quad SPI clock frequency Quad SPI clock high and low time Conditions Min Typ Max 1.71 < VDD < 3.6 V, CLOAD = 20 pF Voltage Range 1 - - 40 2 < VDD < 3.6 V, CLOAD = 20 pF Voltage Range 1 - - 48 1.71 < VDD < 3.6 V, CLOAD = 15 pF Voltage Range 1 - - 48 1.71 < VDD < 3.
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STM32L431xx Electrical characteristics Figure 36. Quad SPI timing diagram - SDR mode WU &. &ORFN W &. WZ &.+ WY 287 WZ &./ WI &. WK 287 'DWD RXWSXW ' ' WV ,1 'DWD LQSXW ' WK ,1 ' ' ' 06Y 9 Figure 37. Quad SPI timing diagram - DDR mode WU &. &ORFN 'DWD RXWSXW W &. WYI 287 WZ &.+ WKU 287 ' WYU 287 ' ' WZ &./ WKI 287 ' WVI ,1 WKI ,1 'DWD LQSXW ' ' WI &. ' ' WVU ,1 WKU ,1 ' ' ' ' 06Y 9 DocID028800 Rev 1 163/200 168 Downloaded from Arrow.com.
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Electrical characteristics STM32L431xx SAI characteristics Unless otherwise specified, the parameters given in Table 85 for SAI are derived from tests performed under the ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized inTable 21: General operating conditions, with the following configuration: • Output speed is set to OSPEEDRy[1:0] = 10 • Capacitive load C = 30 pF • Measurement points are done at CMOS levels: 0.5 ₓ VDD Refer to Section 6.3.
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STM32L431xx Electrical characteristics Table 85. SAI characteristics(1) (continued) Symbol tv(SD_B_ST) th(SD_B_ST) tv(SD_A_MT) th(SD_A_MT) Parameter Conditions Data output valid time Data output hold time Data output valid time Data output hold time Min Max Slave transmitter (after enable edge) 2.7 ≤ VDD ≤ 3.6 - 22 Slave transmitter (after enable edge) 1.71 ≤ VDD ≤ 3.6 - 34 Slave transmitter (after enable edge) 10 - Master transmitter (after enable edge) 2.7 ≤ VDD ≤ 3.
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Electrical characteristics STM32L431xx Figure 39.
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STM32L431xx Electrical characteristics Table 86. SD / MMC dynamic characteristics, VDD=2.7 V to 3.6 V(1) (continued) Symbol Parameter Conditions Min Typ Max Unit CMD, D outputs (referenced to CK) in SD default mode tOVD Output valid default time SD fPP = 50 MHz - 2 3 ns tOHD Output hold default time SD fPP = 50 MHz 0 - - ns 1. Guaranteed by characterization results. Table 87. eMMC dynamic characteristics, VDD = 1.71 V to 1.
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Electrical characteristics STM32L431xx Figure 41. SD default mode #+ T/6$ T/($ $ #-$ OUTPUT AI CAN (controller area network) interface Refer to Section 6.3.14: I/O port characteristics for more details on the input/output alternate function characteristics (CAN_TX and CAN_RX). SWPMI characteristics The Single Wire Protocol Master Interface (SWPMI) and the associated SWPMI_IO transceiver are compliant with the ETSI TS 102 613 technical specification. Table 88.
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STM32L431xx 7 Package information Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. 7.1 LQFP100 package information Figure 42. LQFP100 - 100-pin, 14 x 14 mm low-profile quad flat package outline MM C ! ! ! 3%!4).' 0,!.% # '!5'% 0,!.
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Package information STM32L431xx Table 89. LQPF100 - 100-pin, 14 x 14 mm low-profile quad flat package mechanical data (continued) inches(1) millimeters Symbol Min Typ Max Min Typ Max A2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 D 15.800 16.000 16.200 0.6220 0.6299 0.6378 D1 13.800 14.000 14.200 0.5433 0.5512 0.5591 D3 - 12.000 - - 0.4724 - E 15.800 16.000 16.200 0.6220 0.6299 0.
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STM32L431xx Package information Device marking The following figure gives an example of topside marking orientation versus pin 1 identifier location. Figure 44. LQFP100 marking (package top view) 3URGXFW LGHQWLILFDWLRQ 670 / 2SWLRQDO JDWH PDUN 9&7 $ 5HYLVLRQ FRGH 'DWH FRGH < :: 3LQ LQGHQWLILHU 06Y 9 1.
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Package information 7.2 STM32L431xx UFBGA100 package information Figure 45. UFBGA100 - 100-ball, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array package outline = 6HDWLQJ SODQH GGG = $ $ $ $ $ ( H $ EDOO $ EDOO LGHQWLILHU LQGH[ DUHD ) ; ( $ ) ' ' H < 0 %27720 9,(: E EDOOV HHH 0 = < ; III 0 = 723 9,(: $ & B0(B9 1. Drawing is not to scale. Table 90. UFBGA100 - 100-ball, 7 x 7 mm, 0.
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STM32L431xx Package information Table 90. UFBGA100 - 100-ball, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array package mechanical data (continued) inches(1) millimeters Symbol Min. Typ. Max. Min. Typ. Max. F 0.700 0.750 0.800 0.0276 0.0295 0.0315 ddd - - 0.100 - - 0.0039 eee - - 0.150 - - 0.0059 fff - - 0.050 - - 0.0020 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 46. UFBGA100 - 100-ball, 7 x 7 mm, 0.
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Package information STM32L431xx Figure 47. UFBGA100 marking (package top view) 3URGXFW LGHQWLILFDWLRQ 670 / 9&, < :: 'DWH FRGH $ 3LQ LGHQWLILHU 06Y 9 1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering samples in production.
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STM32L431xx 7.3 Package information LQFP64 package information Figure 48. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package outline PP *$8*( 3/$1( F $ $ $ 6($7,1* 3/$1( & $ FFF & ' ' ' . / / 3,1 ,'(17,),&$7,21 ( ( ( E H :B0(B9 1. Drawing is not to scale. Table 92. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A - - 1.600 - - 0.0630 A1 0.
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Package information STM32L431xx Table 92. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package mechanical data (continued) inches(1) millimeters Symbol Min Typ Max Min Typ Max E3 - 7.500 - - 0.2953 - e - 0.500 - - 0.0197 - K 0° 3.5° 7° 0° 3.5° 7° L 0.450 0.600 0.750 0.0177 0.0236 0.0295 L1 - 1.000 - - 0.0394 - ccc - - 0.080 - - 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 49.
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STM32L431xx Package information Figure 50. LQFP64 marking (package top view) 5HYLVLRQ FRGH $ 3URGXFW LGHQWLILFDWLRQ 670 / 5&7 < :: 'DWH FRGH 3LQ LGHQWLILHU 06Y 9 1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge.
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Package information 7.4 STM32L431xx UFBGA64 package information Figure 51. UFBGA64 – 64-ball, 5 x 5 mm, 0.5 mm pitch ultra profile fine pitch ball grid array package outline = 6HDWLQJ SODQH GGG = $ $ $ $ $ ( H ; $ EDOO $ EDOO LGHQWLILHU LQGH[ DUHD ) ( $ ) ' ' H < + E EDOOV HHH 0 = < ; III 0 = %27720 9,(: 723 9,(: $ B0(B9 1. Drawing is not to scale. Table 93. UFBGA64 – 64-ball, 5 x 5 mm, 0.
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STM32L431xx Package information Table 93. UFBGA64 – 64-ball, 5 x 5 mm, 0.5 mm pitch ultra profile fine pitch ball grid array package mechanical data (continued) inches(1) millimeters Symbol Min Typ Max Min Typ Max A 0.460 0.530 0.600 0.0181 0.0209 0.0236 F 0.700 0.750 0.800 0.0276 0.0295 0.0315 ddd - - 0.080 - - 0.0031 eee - - 0.150 - - 0.0059 fff - - 0.050 - - 0.0020 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 52.
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Package information STM32L431xx Figure 53. UFBGA64 marking (package top view) 3URGXFW LGHQWLILFDWLRQ / & < :: 'DWH FRGH $ 3LQ LGHQWLILHU 06Y 9 1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering samples in production.
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STM32L431xx 7.5 Package information WLCSP64 package information Figure 54. WLCSP64 - 64-ball, 3.141 x 3.127 mm, 0.35 mm pitch wafer level chip scale package outline H EEE = ) * $ 'HWDLO $ H H + * H $ $ $ ) %XPS VLGH 6LGH YLHZ ' %XPS $ HHH = ( $ 2ULHQWDWLRQ UHIHUHQFH E FFF = ; < GGG = = 6HDWLQJ SODQH DDD [ :DIHU EDFN VLGH 'HWDLO $ URWDWHG :/&63 B$ B0(B9 1. Drawing is not to scale. Table 95. WLCSP64 - 64-ball, 3.141 x 3.127 mm, 0.
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Package information STM32L431xx Table 95. WLCSP64 - 64-ball, 3.141 x 3.127 mm, 0.35 mm pitch wafer level chip scale package mechanical data (continued) inches(1) millimeters Symbol Min Typ Max Min Typ Max (3) 0.190 0.220 0.250 0.0075 0.0087 0.0098 D 3.106 3.141 3.176 0.1223 0.1237 0.1250 E 3.092 3.127 3.162 0.1217 0.1231 0.1245 e - 0.350 - - 0.0138 - e1 - 2.450 - - 0.0965 - e2 - 2.450 - - 0.0965 - F - 0.3455 - - 0.0136 - G - 0.3385 - - 0.
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STM32L431xx Package information Device marking The following figure gives an example of topside marking orientation versus ball A1 identifier location. Figure 56. WLCSP64 marking (package top view) 3LQ LGHQWLILHU 3URGXFW LGHQWLILFDWLRQ / 5& < :: $ 5HYLVLRQ FRGH 'DWH FRGH 06Y 9 1.
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Package information 7.6 STM32L431xx WLCSP49 package information Figure 57. WLCSP49 - 49-ball, 3.141 x 3.127 mm, 0.4 mm pitch wafer level chip scale package outline H EEE = ) $ EDOO ORFDWLRQ $ * 'HWDLO $ H ( H H $ ' $ $ %RWWRP YLHZ %XPS VLGH 6LGH YLHZ $ E %XPS )URQW YLHZ $ HHH = = E ( FFF GGG $ 2ULHQWDWLRQ UHIHUHQFH =;< = 'HWDLO $ URWDWHG 6HDWLQJ SODQH DDD [ ' 7RS YLHZ :DIHU EDFN VLGH :/&63 B$ =B0(B9 1. Drawing is not to scale. 184/200 Downloaded from Arrow.
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STM32L431xx Package information Table 97. WLCSP49 - 49-ball, 3.141 x 3.127 mm, 0.4 mm pitch wafer level chip scale package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A 0.525 0.555 0.585 0.0207 0.0219 0.0230 A1 - 0.175 - - 0.0069 - A2 - 0.380 - - 0.0150 - - 0.025 - - 0.0010 - b(3) 0.220 0.250 0.280 0.0087 0.0098 0.0110 D 3.106 3.141 3.176 0.1223 0.1237 0.1250 E 3.092 3.127 3.162 0.1217 0.1231 0.1245 e - 0.400 - - 0.
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Package information STM32L431xx Table 98. WLCSP49 recommended PCB design rules (0.4 mm pitch) Dimension Recommended values Pitch 0.4 Dpad 0.225 mm Dsm 0.290 mm typ. (depends on the soldermask registration tolerance) Stencil opening 0.250 mm Stencil thickness 0.100 mm Device marking The following figure gives an example of topside marking orientation versus ball A1 identifier location. Figure 59.
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STM32L431xx 7.7 Package information LQFP48 package information Figure 60. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package outline C ! ! ! 3%!4).' 0,!.% # MM '!5'% 0,!.% CCC # + ! $ $ , , $ 0). )$%.4)&)#!4)/. % % % B E "?-%?6 1. Drawing is not to scale. DocID028800 Rev 1 187/200 197 Downloaded from Arrow.com.
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Package information STM32L431xx Table 99. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A - - 1.600 - - 0.0630 A1 0.050 - 0.150 0.0020 - 0.0059 A2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 D 8.800 9.000 9.200 0.3465 0.3543 0.3622 D1 6.800 7.000 7.200 0.2677 0.2756 0.2835 D3 - 5.500 - - 0.
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STM32L431xx Package information Figure 61. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package recommended footprint AI D 1. Dimensions are expressed in millimeters. Device marking The following figure gives an example of topside marking orientation versus pin 1 identifier location. Figure 62.
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Package information 7.8 STM32L431xx UFQFPN48 package information Figure 63. UFQFPN48 - 48-lead, 7x7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat package outline 3LQ LGHQWLILHU ODVHU PDUNLQJ DUHD ' $ ( ( 7 GGG $ 6HDWLQJ SODQH E H 'HWDLO < ' ([SRVHG SDG DUHD < ' / & [ SLQ FRUQHU ( 5 W\S 'HWDLO = = $ % B0(B9 1. Drawing is not to scale. 2. All leads/pads should also be soldered to the PCB to improve the lead/pad solder joint life. 3.
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STM32L431xx Package information Table 100. UFQFPN48 - 48-lead, 7x7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A 0.500 0.550 0.600 0.0197 0.0217 0.0236 A1 0.000 0.020 0.050 0.0000 0.0008 0.0020 D 6.900 7.000 7.100 0.2717 0.2756 0.2795 E 6.900 7.000 7.100 0.2717 0.2756 0.2795 D2 5.500 5.600 5.700 0.2165 0.2205 0.2244 E2 5.500 5.600 5.700 0.2165 0.2205 0.2244 L 0.300 0.
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Package information STM32L431xx Figure 65. UFQFPN48 marking (package top view) 670 / 3URGXFW LGHQWLILFDWLRQ &&8 < :: 3LQ LGHQWLILHU 'DWH FRGH $ 5HYLVLRQ FRGH 06Y 9 1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge.
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STM32L431xx Package information Table 101. UFQFPN32 - 32-pin, 5x5 mm, 0.5 mm pitch ultra thin fine pitch quad flat package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A 0.500 0.550 0.600 0.0197 0.0217 0.0236 A1 - - 0.050 - - 0.0020 A3 - 0.152 - - 0.0060 - b 0.180 0.230 0.280 0.0071 0.0091 0.0110 D 4.900 5.000 5.100 0.1929 0.1969 0.2008 D1 3.400 3.500 3.600 0.1339 0.1378 0.1417 D2 3.400 3.500 3.600 0.1339 0.1378 0.1417 E 4.
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Package information STM32L431xx Figure 68. UFQFPN32 marking (package top view) 3URGXFW LGHQWLILFDWLRQ / .& < :: $ 'DWH FRGH 5HYLVLRQ FRGH 3LQ LGHQWLILHU 06Y 9 1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge.
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STM32L431xx 7.10 Package information Thermal characteristics The maximum chip junction temperature (TJmax) must never exceed the values given in Table 21: General operating conditions.
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Package information 7.10.2 STM32L431xx Selecting the product temperature range When ordering the microcontroller, the temperature range is specified in the ordering information scheme shown in Section 8: Part numbering. Each temperature range suffix corresponds to a specific guaranteed ambient temperature at maximum dissipation and, to a specific maximum junction temperature.
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STM32L431xx Package information Assuming the following application conditions: Maximum ambient temperature TAmax = 100 °C (measured according to JESD51-2), IDDmax = 20 mA, VDD = 3.5 V, maximum 20 I/Os used at the same time in output at low level with IOL = 8 mA, VOL= 0.4 V PINTmax = 20 mA × 3.5 V= 70 mW PIOmax = 20 × 8 mA × 0.
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Part numbering 8 STM32L431xx Part numbering Table 103.
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STM32L431xx 9 Revision history Revision history Table 104. Document revision history Date Revision 31-May-2016 1 Changes Initial release. DocID028800 Rev 1 199/200 199 Downloaded from Arrow.com.
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STM32L431xx IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.