Datasheet
DocID027096 Rev 2 99/137
STM32L073xx Electrical characteristics
117
Equation 1: R
AIN
max formula
The formula above (Equation 1) is used to determine the maximum external impedance
allowed for an error below 1/4 of LSB. Here N = 12 (from 12-bit resolution).
C
ADC
(2)
Internal sample and hold
capacitor
---8pF
t
CAL
(2)(3)
Calibration time
f
ADC
= 16 MHz 5.2 µs
-831/f
ADC
W
LATENCY
(4)
ADC_DR register write
latency
ADC clock = HSI16
1.5 ADC
cycles + 2
f
PCLK
cycles
-
1.5 ADC
cycles + 3
f
PCLK
cycles
-
ADC clock = PCLK/2 - 4.5 -
f
PCLK
cycle
ADC clock = PCLK/4 - 8.5 -
f
PCLK
cycle
t
latr
(2)
Trigger conversion latency
f
ADC
= f
PCLK
/2 = 16 MHz 0.266 µs
f
ADC
= f
PCLK
/2 8.5 1/f
PCLK
f
ADC
= f
PCLK
/4 = 8 MHz 0.516 µs
f
ADC
= f
PCLK
/4 16.5 1/f
PCLK
f
ADC
= f
HSI16
= 16 MHz 0.252 - 0.260 µs
Jitter
ADC
ADC jitter on trigger
conversion
f
ADC
= f
HSI16
-1-1/f
HSI16
t
S
(2)
Sampling time
f
ADC
= 16 MHz 0.093 - 10 µs
- 1.5 - 160.5 1/f
ADC
t
UP_LDO
(2)(3)
Internal LDO power-up time - - - 10 µs
t
STAB
(2)(3)
ADC stabilization time - 14 1/f
ADC
t
ConV
(2)
Total conversion time
(including sampling time)
f
ADC
= 16 MHz,
12-bit resolution
1-10.13µs
12-bit resolution
14 to 162 (t
S
for sampling +12.5
for successive approximation)
1/f
ADC
1. A current consumption proportional to the APB clock frequency has to be added (see Table 40: Peripheral current
consumption in Run or Sleep mode).
2. Guaranteed by design.
3. This parameter only includes the ADC timing. It does not take into account register access latency.
4. This parameter specifies the latency to transfer the conversion result into the ADC_DR register. EOC bit is set to indicate the
conversion is complete and has the same latency.
Table 64. ADC characteristics (continued)
Symbol Parameter Conditions Min Typ
Max Unit
R
AIN
T
S
f
ADC
C
ADC
2
N2+
()ln××
--------------------------------------------------------------
R
ADC
–<
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